This paper focuses on low-power and low-slew clock network design and analysis for
through-silicon via (TSV) based three-dimensional stacked ICs (3D ICs). First, we investigate …

Incremental static timing analysis (iSTA) is the backbone of iterative sizing and Vt-swap**
heuristics for post-layout timing recovery and leakage power reduction. Performing such …

The traditional purpose of physical synthesis is to perform timing closure, ie, to create a
placed design that meets its timing specifications while also satisfying electrical, routability …

Pre-bond testing of 3D stacked ICs involves testing individual dies before bonding. The
overall yield of 3D ICs improves with prebond testability because designers can avoid …

As very large scale integration technology scales to deep submicrometer and beyond,
interconnect delay greatly limits the circuit performance. The traditional 2-D global routing …

As VLSI technology continuously scales down, buffered clock tree synthesis (CTS) has
become increasingly critical in an attempt to generate a high-performance synchronous chip …

Pre-bond testing of 3-D stacked integrated circuits (ICs) involves testing each individual die
before bonding. The overall yield of 3-D ICs improves with pre-bond testability because …

In this paper, three effective design techniques are presented to effectively reduce the clock
power consumption and slew of the 3D clock distribution network:(1) controlling the bound of …

As technology scaling advances beyond 65 nanometer node, more devices can fit onto a
chip, which implies continued growth of design size. The increased wire delay dominance …

The obstacle-avoiding rectilinear Steiner minimal tree (OARSMT) problem is a hot topic in
very-large-scale integration physical design. In practice, most of the obstacles occupy the …