Adaptive Image Size Padding for Load Balancing in System-on-Chip Memory Hierarchy
SY Kim, JY Hur - Electronics, 2023 - mdpi.com
The conventional address map often incurs traffic congestion in on-chip memory
components and degrades memory utilization when the access pattern of an application is …
components and degrades memory utilization when the access pattern of an application is …
Compute-In-Memory-Based Floating-Point Processor
2024-02-05 Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
reassignment TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD …
reassignment TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD …
Apparatus and method with graphics processing
Y Shin, CHO Yeongon - US Patent App. 17/572,755, 2022 - Google Patents
An apparatus with graphics processing includes: a memory configured to store therein
acceleration structure data and primitive data for performing three-dimensional (3D) …
acceleration structure data and primitive data for performing three-dimensional (3D) …
Hardware-software collaborative address map** scheme for efficient processing-in-memory systems
Approaches are provided for implementing hardware-software collaborative address
map** schemes that enable map** data elements which are accessed together in the …
map** schemes that enable map** data elements which are accessed together in the …