Measuring the gap between FPGAs and ASICs

I Kuon, J Rose - Proceedings of the 2006 ACM/SIGDA 14th …, 2006 - dl.acm.org
This paper presents experimental measurements of the differences between a 90nm CMOS
FPGA and 90nm CMOS Standard Cell ASICs in terms of logic density, circuit speed and …

Temperature and supply voltage aware performance and power modeling at microarchitecture level

W Liao, L He, KM Lepak - IEEE Transactions on Computer …, 2005 - ieeexplore.ieee.org
Performance and power are two primary design issues for systems ranging from server
computers to handhelds. Performance is affected by both temperature and supply voltage …

Accurate stacking effect macro-modeling of leakage power in sub-100 nm circuits

S Yang, W Wolf, N Vijaykrishnan, Y **e… - … Conference on VLSI …, 2005 - ieeexplore.ieee.org
An accurate and efficient stacking effect macro-model for leakage power in sub-100 nm
circuits is presented in this paper. Leakage power, including subthreshold leakage power …

Microarchitecture level power and thermal simulation considering temperature dependent leakage model

W Liao, F Li, L He - Proceedings of the 2003 international symposium on …, 2003 - dl.acm.org
In this paper, we present power models with clock and temperature scaling, and develop the
first of its type coupled thermal and power simulation with temperature-dependent leakage …

Contract representation for run-time monitoring and enforcement

C Molina-Jimenez, S Shrivastava… - … Conference on E …, 2003 - ieeexplore.ieee.org
Converting a conventional contract into an electronic equivalent that can be executed and
enforced by computers is a challenging task. The difficulties are caused by the ambiguities …

[PDF][PDF] Leakage power estimation in SRAMs

M Mamidipaka, K Khouri, N Dutt, M Abadir - Univ. of Cal. Irvine CECS …, 2003 - Citeseer
In this paper we propose analytical models for estimating the leakage power in CMOS
based SRAM designs. We identify the transistors that contribute to the leakage power in …

Leakage and leakage sensitivity computation for combinational circuits

E Acar, A Devgan, R Rao, Y Liu, H Su… - Proceedings of the …, 2003 - dl.acm.org
Leakage power is emerging as a new critical challenge in the design of high performance
integrated circuits. Leakage is increasing dramatically with each technology generation and …

Defocus-aware leakage estimation and control

AB Kahng, S Muddu, P Sharma - … of the 2005 international symposium on …, 2005 - dl.acm.org
Leakage power is one of the most critical issues for ultra-deep submicron technology.
Subthreshold leakage depends exponentially on linewidth, and consequently variation in …

[PDF][PDF] Temperature-aware performance and power modeling

W Liao, L He, K Lepak - UCLA, Los Angeles, CA, Tech. Rep. UCLA Eng, 2004 - Citeseer
Power has become the primary design constraint for systems ranging from server computers
to handhelds. As semiconductor technology scales down, leakage power becomes …

Band-to-band-tunneling leakage suppression for ultra-thin-body GeOI MOSFETs using transistor stacking

VPH Hu, ML Fan, P Su… - IEEE electron device letters, 2012 - ieeexplore.ieee.org
This letter indicates that the ultra-thin-body (UTB) germanium-on-insulator (GeOI) MOSFETs
preserve the leakage reduction property of stacking devices, while the band-to-band …