In the last five decades, the number of transistors on a chip has increased exponentially in
accordance with the Moore's law, and the semiconductor industry has followed this law as …

Placement is an important step in modern verylarge-scale integrated (VLSI) designs.
Detailed placement is a placement refining procedure intensively called throughout the …

As very large-scale integration technology shrinks to fewer tracks per standard cell, eg, from
10 to 7.5-track libraries (and lesser for 7 nm), there has been a rapid increase in the usage …

The layouts of analog/mixed-signal (AMS) integrated circuits (ICs) are dramatically different
from their digital counterparts. AMS circuit layouts usually include a variety of devices …

Integrated circuits are present in a diversity of electronic applications around us. We can find
them in a wide spectrum of consumer applications like smartphones, iPods, video games …

Layout-dependent effect causes variation in device performance as well as mismatch in
model-hardware correlation in sub-10 nm nodes. In order to effectively explore the power …

In multiple electron beam lithography (MEBL), a layout is split into stripes and the layout
patterns are cut by stripe boundaries, then all the stripes are printed in parallel. If a via …

In sub-10nm, nodes, a change or step in diffusion height between adjacent standard cells
causes yield loss as well as a form of model-hardware miscorrelation called neighbor …

FinFET technology is an attractive candidate for high-performance and power-efficient
application and is currently used for several electronic products. FinFET technology …

Aggressive pitch scaling in sub-10nm nodes has introduced complex design rules which
make routing extremely challenging. Cell architectures have also been changed to meet the …