We consider the problem of computing a binary linear transformation when all circuit
components are unreliable. Two models of unreliable components are considered …

This paper investigates the behavior of the Min-Sum decoder running on noisy devices. Our
aim is to evaluate the robustness of the decoder to computation noise caused by the faulty …

Computing systems are evolving rapidly. At the device level, emerging devices are
beginning to compete with traditional CMOS systems. At the architecture level, novel …

The wide recognition that emerging nano-devices will be inherently unreliable motivates the
evaluation of information processing algorithms running on noisy hardware as well as the …

In this letter, we characterize the effect of data-dependent gate failures on the performance
of the Gallager B decoder of low-density parity-check codes. We show that this type of …

This paper addresses the problem of designing low-density parity check decoders robust to
transient errors introduced by faulty hardware. We assume that the faulty hardware …

This paper proposes a “quasi-synchronous” design approach for signal processing circuits,
in which timing violations are permitted, but without the need for a hardware compensation …

In this paper we summarize recent results and contributions from the NSF Expedition on
Variability-Aware Software, a five year, multi-university effort to tackle the problem of …

In this paper, we investigate the decoding performance of spatially-coupled LDPC codes in
the case of faulty memory bit-cells within the storage modules of the decoder. Our study …

The objective of this paper is to minimize the energy consumption of a quantized Min-Sum
LDPC decoder, by considering aggressive voltage downscaling of the decoder circuit. Since …