[書籍][B] Low-power electronics design

C Piguet - 2018 - books.google.com
The power consumption of integrated circuits is one of the most problematic considerations
affecting the design of high-performance chips and portable devices. The study of power …

New clock-gating techniques for low-power flip-flops

AGM Strollo, E Napoli, D De Caro - Proceedings of the 2000 …, 2000 - dl.acm.org
Two novel low power flip-flops are presented in the paper. Proposed flip-flops use new
gating techniques that reduce power dissipation deactivating the clock signal. Presented …

Low-power design techniques for scaled technologies

BC Paul, A Agarwal, K Roy - Integration, 2006 - Elsevier
Scaling of transistor feature sizes has provided a remarkable advancement in silicon
industry for last three decades. However, while the performance increases due to scaling …

Clock gating and clock enable for FPGA power reduction

JP Oliver, J Curto, D Bouvier, M Ramos… - 2012 VIII Southern …, 2012 - ieeexplore.ieee.org
This paper presents experimental measurements of power consumption using different
techniques to turn off part of a system and switch between active and standby modes. The …

Between globalization and local 'Modernity': The diffusion and modernization of football in Algeria

M Amara, I Henry - Soccer & Society, 2004 - Taylor & Francis
This article highlights the importance of football in Algeria as a cultural and political vehicle;
a) during the colonial period as a mean of resisting western (colonial) hegemony; b) in the …

Low-power flip-flops with reliable clock gating

AGM Strollo, E Napoli, D De Caro - Microelectronics journal, 2001 - Elsevier
The paper presents two gated flip-flops aimed at low-power applications. The proposed flip-
flops use new gating techniques that reduce power dissipation deactivating the clock signal …

[PDF][PDF] Power-aware scheduling of data-flow hardware circuits with symbolic control

M Özbaltan, N Berthier - Archives of Control Sciences, 2021 - bibliotekanauki.pl
We devise a tool-supported framework for achieving power-efficiency of data-flow hardware
circuits. Our approach relies on formal control techniques, where the goal is to compute a …

Exercising symbolic discrete control for designing low-power hardware circuits: an application to clock-gating

M Özbaltan, N Berthier - IFAC-PapersOnLine, 2018 - Elsevier
We devise a tool-supported framework for achieving power-efficiency of hardware chips
from high-level designs described using the popular hardware description language Verilog …

Method for finding multi-cycle clock gating

CR Eisner, M Farkash - US Patent 7,594,200, 2009 - Google Patents
An apparatus includes a multi-cycle clock gater and a circuit design updater. The multi-cycle
clock gater generates multi cycle gating groups of data latching devices of a circuit design …

Power optimization of an 8051-compliant IP microcontroller

L Fanucci, S Saponara, A Morello - IEICE Transactions on …, 2005 - search.ieice.org
Several IP cells are available in the market to implement 8051-compliant microcontroller in
embedded systems. Yet they frequently lack features that have become a key point in such …