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2-D Analytical Drain Current Model of Double-Gate Heterojunction TFETs With a SiO2/HfO2 Stacked Gate-Oxide Structure
A continuous 2-D analytical drain current model of double-gate (DG) heterojunction tunnel
field-effect transistors (HJTFETs) with a SiO 2/HfO 2 stacked gate-oxide structures has been …
field-effect transistors (HJTFETs) with a SiO 2/HfO 2 stacked gate-oxide structures has been …
Investigation of negative capacitance gate-all-around tunnel FETs combining numerical simulation and analytical modeling
A short-channel negative capacitance gate-all-around tunnel field-effect transistor (NC-GAA-
TFET) with a ferroelectric gate stack is proposed. Device performance is investigated by …
TFET) with a ferroelectric gate stack is proposed. Device performance is investigated by …
A compact model for double-gate heterojunction tunnel FETs
A compact model for generic heterojunction tunnel FETs (H-TFET) is developed to simulate
H-TFET formed by different source/body material systems. The model is based on the device …
H-TFET formed by different source/body material systems. The model is based on the device …
An analytical model of drain current in a nanoscale circular gate TFET
This paper presents an analytical model of drain current in a silicon tunnel FET with a
circular gate (CG TFET). The method involves the bifurcation of the complete geometry into a …
circular gate (CG TFET). The method involves the bifurcation of the complete geometry into a …
An accurate analytical current model of double-gate heterojunction tunneling FET
Y Guan, Z Li, W Zhang, Y Zhang - IEEE Transactions on …, 2017 - ieeexplore.ieee.org
A continuous accurate analytical drain current model considering the effect of the inversion
charge is presented for the double-gate heterojunction tunneling FET. The band-to-band …
charge is presented for the double-gate heterojunction tunneling FET. The band-to-band …
An analytical model of gate-all-around heterojunction tunneling FET
Y Guan, Z Li, W Zhang, Y Zhang… - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
A compact analytical drain current model considering the inversion layer and source
depletion is developed for the gate-all-around (GAA) heterojunction tunneling FET (H-TFET) …
depletion is developed for the gate-all-around (GAA) heterojunction tunneling FET (H-TFET) …
Emerging steep-slope devices and circuits: Opportunities and challenges
While continuing the CMOS scaling-down becomes unprecedentedly more challenging than
before, intensive exploration on beyond-CMOS nanodevice technologies is an appealing …
before, intensive exploration on beyond-CMOS nanodevice technologies is an appealing …
A charge-based capacitance model for double-gate tunnel FETs with closed-form solution
Based on an analytical surface potential and a simple mathematical approximation for the
source depletion width, a physics-based capacitance model with closed form for silicon …
source depletion width, a physics-based capacitance model with closed form for silicon …
Device reliability of negative capacitance source pocket double gate TFETs: a study on temperature and noise effects
This study investigates the reliability of a negative capacitance source pocket double gate
tunnel field-effect transistor (NC-SP-DGTFET) by examining the effects of temperature and …
tunnel field-effect transistor (NC-SP-DGTFET) by examining the effects of temperature and …
Analytical model of a novel double gate metal-infused stacked gate-oxide tunnel field-effect transistor (TFET) for low power and high-speed performance
In this work, an innovative structure of a novel double gate tunnel field-effect transistor
(TFET) is proposed with a channel length of 20 nm. The gate dielectric regions have been …
(TFET) is proposed with a channel length of 20 nm. The gate dielectric regions have been …