The detection of small-delay faults is traditionally performed by sensitizing transitions on a
path of sufficient length from an input to an output of the circuit going through the fault site …

Testing for small-delay defects (SDDs) requires fault-effect propagation along the longest
testable paths. However, identification of the longest testable paths requires high CPU time …

An efficient degraded deductive simulator for small delay defects is proposed. The proposed
method takes into account the conditions of re-convergence sensitization and hazard-based …

This letter proposes an algorithm that selects a small number of test patterns for small delay
defects from a large N-detect test set. This algorithm uses static upper and lower bound …

The population of small-delay defects (SDDs) in integrated circuits increases significantly as
technology scales to 65 nm and below. Therefore, testing for SDDs is necessary to ensure …

This article presents a brief survey of digital delay fault testing, which lists 100+ references
on fault models, simulators, ATPG, DFT, and tools. Continuing studies are needed in this …

Functional microprocessor test methods provide several advantages compared to DFT
approaches, like reduced chip cost and at-speed execution. However, the automatic …

For sub-nanometer designs, testing for small-delay defects (SDDs) is essential to achieve
low defect escapes for the manufactured silicon. Existing solutions for testing SDDs are not …

Testing for small-delay defects (SDDs) is necessary to ensure the quality and reliability of
high-performance integrated circuits fabricated with the latest technologies. These timing …

This paper presents silicon results for two such proposed fault models: the cell aware fault
model and the small delay defect fault model. The corresponding tests including cell-aware …