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Specification and verification of side-channel security for open-source processors via leakage contracts
Leakage contracts have recently been proposed as a new security abstraction at the
Instruction Set Architecture (ISA) level. Leakage contracts aim to capture the information that …
Instruction Set Architecture (ISA) level. Leakage contracts aim to capture the information that …
Hide and Seek with Spectres: Efficient discovery of speculative information leaks with random testing
Attacks like Spectre abuse speculative execution, one of the key performance optimizations
of modern CPUs. Recently, several testing tools have emerged to automatically detect …
of modern CPUs. Recently, several testing tools have emerged to automatically detect …
Pensieve: Microarchitectural modeling for security evaluation
Traditional modeling approaches in computer architecture aim to obtain an accurate
estimation of performance, area, and energy of a processor design. With the advent of …
estimation of performance, area, and energy of a processor design. With the advent of …
Serberus: Protecting cryptographic code from spectres at compile-time
We present Serberus, the first comprehensive mitigation for hardening constant-time (CT)
code against Spectre attacks (involving the PHT, BTB, RSB, STL, and/or PSF speculation …
code against Spectre attacks (involving the PHT, BTB, RSB, STL, and/or PSF speculation …
Microprofiler: Principled side-channel mitigation through microarchitectural profiling
Preventing information leakage through microarchitectural side channels is notoriously
challenging and, as a result, an important research question. Recent work has shown the …
challenging and, as a result, an important research question. Recent work has shown the …
Conjunct: Learning inductive invariants to prove unbounded instruction safety against microarchitectural timing attacks
The past decade has seen a deluge of microarchitectural side channels stemming from a
variety of hardware structures (the cache, branch predictor, execution ports, the TLB …
variety of hardware structures (the cache, branch predictor, execution ports, the TLB …
Zeroleak: Using llms for scalable and cost effective side-channel patching
Security critical software, eg, OpenSSL, comes with numerous side-channel leakages left
unpatched due to a lack of resources or experts. The situation will only worsen as the pace …
unpatched due to a lack of resources or experts. The situation will only worsen as the pace …
Modular Verification of Secure and Leakage-Free Systems: From Application Specification to Circuit-Level Implementation
Parfait is a framework for proving that an implementation of a hardware security module
(HSM) leaks nothing more than what is mandated by an application specification. Parfait …
(HSM) leaks nothing more than what is mandated by an application specification. Parfait …
Perspective: A principled framework for pliable and secure speculation in operating systems
Transient execution attacks present an unprecedented threat to computing systems.
Protecting the operating system (OS) is exceptionally challenging because a transient …
Protecting the operating system (OS) is exceptionally challenging because a transient …
Architectural Mimicry: Innovative Instructions to Efficiently Address Control-Flow Leakage in Data-Oblivious Programs
The control flow of a program can often be observed through side-channel attacks. Hence,
when control flow depends on secrets, attackers can learn information about these secrets …
when control flow depends on secrets, attackers can learn information about these secrets …