This paper presents the ITC'02 SOC test benchmarks. The purpose of this new benchmark
set is to stimulate research into new methods and tools for modular testing of SOCs and to …

At-speed testing of gigahertz processors using external testers may not be technically and
economically feasible. Hence, there is an emerging need for low-cost high-quality self-test …

This paper presents a new compression method for embedded core-based system-on-a-
chip test. In addition to the new compression method, this paper analyzes the three test data …

The programmable cores on SoCs can perform on-chip test generation, measurement,
response analysis, and even diagnosis. This software-based approach to self-testing …

In this paper a novel architecture for scan-based mixed mode BIST is presented. To reduce
the storage requirements for the deterministic patterns it relies on a two-dimensional …

Scan based test techniques offer a very efficient alternative to achieve high fault coverage
when compared to functional pattern testing. As circuit sizes grow ever larger, test data …

We present a technique for making a circuit ready for logic BIST by masking unknown values
at its outputs. In order to keep the silicon area cost low, some known bits in output responses …

Reducing test application time and test data volume are major challenges in SoC design. In
the case of IP cores, where no structural information is available, a common strategy is to …

The built-in stress test (BIST) is extensively used for diagnostics or identification of failure.
The current version of BIST approach is focused on reactive failure detection and provides …

This paper presents a new test data-compression scheme that is a hybrid approach between
external testing and built-in self-test (BIST). The proposed approach is based on weighted …