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[HTML][HTML] Integrated on-chip transformers: recent progress in the design, layout, modeling and fabrication
On-chip transformers are considered to be the primary components in many RF wireless
applications. This paper provides an in-depth review of on-chip transformers, starting with a …
applications. This paper provides an in-depth review of on-chip transformers, starting with a …
Wafer-Level Fabricated Tight-Coupling Dual-Solenoid Transformer Chips With Watt-Scale Power Transfer
C Chen, P Pan, D Lyu, J Gu, M Liu… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
Reported are a novel kind of tight-coupled dual-solenoid transformers (DSTs) which are on-
chip integrated by using wafer-level fabrication including a low melting-point zinc-aluminum …
chip integrated by using wafer-level fabrication including a low melting-point zinc-aluminum …
CMOS negative impedance converter circuit with the elimination of parasitic gate-source capacitance
S Durukan, O Palamutçuoğullari… - 2022 Microwave …, 2022 - ieeexplore.ieee.org
A CMOS negative impedance converter (NIC) circuit with the cross-coupled topology is
designed to generate negative resistance/capacitance/inductance in the frequency range …
designed to generate negative resistance/capacitance/inductance in the frequency range …
Design and implementation of LTCC coreless transformers for intelligent solid-state switch
Y Lu, Z Huang, C Chen, H Tang, L Shi… - Microelectronics Journal, 2022 - Elsevier
This paper designs, manufactures, and evaluates a multilayer coreless low temperature
coiffed ceramic (LTCC) transformer for solid state power controller (SSPC) applications. A …
coiffed ceramic (LTCC) transformer for solid state power controller (SSPC) applications. A …
[PDF][PDF] CMOS non-Foster Circuit Design Using 0.35 μm BiCMOS Models by Cancelling the Parasitic Capacitances
S Durukan, O Palamutçuoğulları - avestia.com
In this paper, an improved type of CMOS non-Foster circuit with the cross-coupled pair is
proposed to produce negative resistance, negative capacitance and negative inductance in …
proposed to produce negative resistance, negative capacitance and negative inductance in …
Intrinsic stress-induced self-assembly of multilayer thin films for fabrication of three-dimensional micro devices
R Bajwa - 2018 - research.sabanciuniv.edu
This work reports on the process technology development for fabrication of three-
dimensional (3D), on-chip micro devices based on self-assembly using intrinsic stresses …
dimensional (3D), on-chip micro devices based on self-assembly using intrinsic stresses …
Negatif empedans dönüştürücü devrelerinin analizi, tasarımı ve pratik uygulamaları
S Durukan - 2022 - search.proquest.com
Elektronik devre ve sistemlerin geliĢimi iki ana kol üzerinden olmaktadır. Bunlardan biri
aktif/yarıiletken malzemeler ve pasif devre elemanları üzerinde yapılan yenilikçi ve …
aktif/yarıiletken malzemeler ve pasif devre elemanları üzerinde yapılan yenilikçi ve …