Evaluation of dynamic triple modular redundancy in an interleaved-multi-threading risc-v core
Functional safety is a key requirement in several application domains in which
microprocessors are an essential part. A number of redundancy techniques have been …
microprocessors are an essential part. A number of redundancy techniques have been …
Dynamic triple modular redundancy in interleaved hardware threads: An alternative solution to lockstep multi-cores for fault-tolerant systems
Over the years, significant work has been done on high-integrity systems, such as those
found in cars, satellites and aircrafts, to minimize the risk that a logic fault causes a system …
found in cars, satellites and aircrafts, to minimize the risk that a logic fault causes a system …
A flexible tensor block coordinate ascent scheme for hypergraph matching
The estimation of correspondences between two images resp. point sets is a core problem
in computer vision. One way to formulate the problem is graph matching leading to the …
in computer vision. One way to formulate the problem is graph matching leading to the …
Warped-DMR: Light-weight error detection for GPGPU
General purpose graphics processing units (GPGPUs) are feature rich GPUs that provide
general purpose computing ability with massive number of parallel threads. The massive …
general purpose computing ability with massive number of parallel threads. The massive …
GangES: Gang error simulation for hardware resiliency evaluation
As technology scales, the hardware reliability challenge affects a broad computing market,
rendering traditional redundancy based solutions too expensive. Software anomaly based …
rendering traditional redundancy based solutions too expensive. Software anomaly based …
Robust indoor wireless localization using sparse recovery
With the multi-antenna design of WiFi interfaces, phased array has become a promising
mechanism for accurate WiFi localization. State-of-the-art WiFi-based solutions using AoA …
mechanism for accurate WiFi localization. State-of-the-art WiFi-based solutions using AoA …
Architectural simulators considered harmful
Much as Edgar Dijkstra in 1968 observed the dangers of relying on the" go to" statement, the
authors of this article observe the detrimental effect of overreliance on quantitative …
authors of this article observe the detrimental effect of overreliance on quantitative …
A survey of checker architectures
Reliability is quickly becoming a primary design constraint for high-end processors because
of the inherent limits of manufacturability, extreme miniaturization of transistors, and the …
of the inherent limits of manufacturability, extreme miniaturization of transistors, and the …
[PDF][PDF] Analysis and modeling of memory errors from large-scale field data collection
Main memory reliability plays a crucial role in overall system reliability. Unfortunately, our
collective understanding of the rate, pattern, and impact of memory errors is inadequate and …
collective understanding of the rate, pattern, and impact of memory errors is inadequate and …
Low cost concurrent error masking using approximate logic circuits
MR Choudhury, K Mohanram - IEEE Transactions on computer …, 2013 - ieeexplore.ieee.org
With technology scaling, logical errors arising due to single-event upsets and timing errors
arising due to dynamic variability effects are increasing in logic circuits. Existing techniques …
arising due to dynamic variability effects are increasing in logic circuits. Existing techniques …