Evaluation of dynamic triple modular redundancy in an interleaved-multi-threading risc-v core

M Barbirotta, A Cheikh, A Mastrandrea… - Journal of Low Power …, 2022 - mdpi.com
Functional safety is a key requirement in several application domains in which
microprocessors are an essential part. A number of redundancy techniques have been …

Dynamic triple modular redundancy in interleaved hardware threads: An alternative solution to lockstep multi-cores for fault-tolerant systems

M Barbirotta, F Menichelli, A Cheikh… - IEEE …, 2024 - ieeexplore.ieee.org
Over the years, significant work has been done on high-integrity systems, such as those
found in cars, satellites and aircrafts, to minimize the risk that a logic fault causes a system …

A flexible tensor block coordinate ascent scheme for hypergraph matching

Q Nguyen, A Gautier, M Hein - Proceedings of the IEEE …, 2015 - openaccess.thecvf.com
The estimation of correspondences between two images resp. point sets is a core problem
in computer vision. One way to formulate the problem is graph matching leading to the …

Warped-DMR: Light-weight error detection for GPGPU

H Jeon, M Annavaram - 2012 45th Annual IEEE/ACM …, 2012 - ieeexplore.ieee.org
General purpose graphics processing units (GPGPUs) are feature rich GPUs that provide
general purpose computing ability with massive number of parallel threads. The massive …

GangES: Gang error simulation for hardware resiliency evaluation

SK Sastry Hari, R Venkatagiri, SV Adve… - ACM SIGARCH …, 2014 - dl.acm.org
As technology scales, the hardware reliability challenge affects a broad computing market,
rendering traditional redundancy based solutions too expensive. Software anomaly based …

Robust indoor wireless localization using sparse recovery

W Gong, J Liu - 2017 IEEE 37th International Conference on …, 2017 - ieeexplore.ieee.org
With the multi-antenna design of WiFi interfaces, phased array has become a promising
mechanism for accurate WiFi localization. State-of-the-art WiFi-based solutions using AoA …

Architectural simulators considered harmful

T Nowatzki, J Menon, CH Ho, K Sankaralingam - IEEE Micro, 2015 - ieeexplore.ieee.org
Much as Edgar Dijkstra in 1968 observed the dangers of relying on the" go to" statement, the
authors of this article observe the detrimental effect of overreliance on quantitative …

A survey of checker architectures

R Kalayappan, SR Sarangi - ACM Computing Surveys (CSUR), 2013 - dl.acm.org
Reliability is quickly becoming a primary design constraint for high-end processors because
of the inherent limits of manufacturability, extreme miniaturization of transistors, and the …

[PDF][PDF] Analysis and modeling of memory errors from large-scale field data collection

T Siddiqua, AE Papathanasiou, A Biswas… - SELSE, 2013 - Citeseer
Main memory reliability plays a crucial role in overall system reliability. Unfortunately, our
collective understanding of the rate, pattern, and impact of memory errors is inadequate and …

Low cost concurrent error masking using approximate logic circuits

MR Choudhury, K Mohanram - IEEE Transactions on computer …, 2013 - ieeexplore.ieee.org
With technology scaling, logical errors arising due to single-event upsets and timing errors
arising due to dynamic variability effects are increasing in logic circuits. Existing techniques …