This book provides broad and comprehensive coverage of the entire EDA flow. EDA/VLSI
practitioners and researchers in need of fluency in an" adjacent" field will find this an …

The development of very large-scale integration (VLSI) technology has posed new
challenges for electronic design automation (EDA) techniques in chip floorplanning. During …

Large macro blocks, predesigned datapaths, embedded memories, and analog blocks are
increasingly used in application-specific integrated circuit (ASIC) designs. However, robust …

While recent literature on circuit layout addresses large-scale standard-cell placement, the
authors typically assume that all macros are fixed. Floorplanning techniques are very good …

As the technology node advances into the nanometer era, via-open defects are one of the
dominant failures due to the copper cladding process. To improve via yield and reliability …

In this paper, we propose a fixed-outline floorplanning (FOFP) method [insertion-after-
remove (IAR) FP]. An elaborated method for perturbing solutions, the IAR, is devised. This …

Research in floorplanning and block-packing has generated a variety of data structures to
represent spatial configurations of circuit modules. Much of this work focuses on the …

As nanometer technology advances, the post chemical-mechanical polishing (CMP)
topography variation control becomes crucial for manufacturing closure. To improve the …

Physical Design of modern systems on chip is extremely challenging. Such digital integrated
circuits often contain tens of millions of logic gates, intellectual property blocks, embedded …

mPL6 consists of three basic ingredients: global placement by multilevel nonlinear
programming [21], discrete graph-based macro legalization followed by linear-time scan …