Optimization-based power and thermal management for dark silicon aware 3D chip multiprocessors using heterogeneous cache hierarchy
Management of a problem recently known as “dark silicon” is a new challenge in multicore
designs. Prior innovative studies have addressed the dark silicon problem in the fields of …
designs. Prior innovative studies have addressed the dark silicon problem in the fields of …
A HDL based reduced area NOC router architecture
MS Suraj, D Muralidharan… - … Conference on Emerging …, 2013 - ieeexplore.ieee.org
In this work, we present the NOC router architecture with five port support which utilizes dual
crossbar arrangement, the latency which arises due to the dual cross bar architecture is …
crossbar arrangement, the latency which arises due to the dual cross bar architecture is …
[PDF][PDF] Centralized Adaptive Source-Routing for Networks-on-Chip as HW/SW-Solution with Cluster-based Workload Isolation
P Gorski, C Cornelius… - 8th International …, 2013 - amd.e-technik.uni-rostock.de
The growing number of applications and processing units in modern MPSoCs comes along
with dynamic and diverse workload characteristics at runtime. Thus, the communication …
with dynamic and diverse workload characteristics at runtime. Thus, the communication …
[PDF][PDF] A power efficient NoC router design
In this work, we present the NOC router architecture with five port support which utilizes dual
crossbar arrangement, the latency which arises due to the dual cross bar architecture is …
crossbar arrangement, the latency which arises due to the dual cross bar architecture is …
[PDF][PDF] A fuzzy-based performance-enhancing input selection technique for network-on-chip
The performance of network-on-chip (NOC) largely depends on the underlying routing
techniques. A routing technique has two constituencies: output selection and input selection …
techniques. A routing technique has two constituencies: output selection and input selection …
[PDF][PDF] Run-time thermal management based on task migration techniques in 3D chip multiprocessors
SO Aljeddani - 2018 - rshare.library.torontomu.ca
By Sulaiman Obaid Aljeddani Master of Applied Science, Electrical and Computer
Engineering Ryerson University, Toronto, 2018. The industry trend of Chip Multiprocessors …
Engineering Ryerson University, Toronto, 2018. The industry trend of Chip Multiprocessors …
ICAIS: Improved Contention Aware Input Selection Technique to increase routing efficiency for Network-On-Chip
Abstract Network-on-Chip (NoC) has been proposed as a solution to provide better
modularity, scalability, reliability and higher bandwidth compared to bus-based …
modularity, scalability, reliability and higher bandwidth compared to bus-based …
A new fuzzy input selection technique to increase routing efficiency for Network-On-Chip
The performance of Network-On-Chip (NOC) largely depends on the underlying routing
techniques. A routing technique has two constituencies: output selection and input selection …
techniques. A routing technique has two constituencies: output selection and input selection …
[引用][C] FPASR: A NEW EFFICIENT FUZZY POWER-AWARE SOURCE ROUTING ALGORITHM FOR NETWORK-ON-CHIP
EB NEJAD, H MEHDI, A EINIPOUR