[HTML][HTML] Triple and quadruple metal gate work function engineering to improve the performance of junctionless double surrounding gate In0. 53Ga0. 47As nanotube …

V Kumar, A Vohra - Physics Letters A, 2024 - Elsevier
In line with Moore's Law and the International Roadmap for Devices and Systems (IDRS),
shrinking MOSFET dimensions to the 3 nm technology node requires the introduction and …

A machine learning approach to accelerate reliability prediction in nanowire FETs from self-heating perspective

TS Kumar, A Hazarika, P Srinivas, PK Tiwari… - Microelectronics …, 2024 - Elsevier
Abstract Nanowire Field Effect Transistors (NWFETs) have been considered as the next-
generation technology for sub-10 nm technology nodes, succeeding FinFETs. However, the …

Temperature sensitivity of GaSb/Si/SiGe heterojunction vertical nanowire junctionless field-effect transistor for logic circuit applications

A Thakur, MC Pedapudi, N Shrivastva, P Mani… - Micro and …, 2025 - Elsevier
In this article, a GaSb/Si/SiGe heterojunction vertical nanowire (V-NW) junctionless field-
effect transistors (JFETs) under the influence of elevated temperature have been …