Dynamic storage allocation: A survey and critical review
PR Wilson, MS Johnstone, M Neely, D Boles - … Workshop IWMM 95 …, 1995 - Springer
Dynamic memory allocation has been a fundamental part of most computer systems since
roughly 1960, and memory allocation is widely considered to be either a solved problem or …
roughly 1960, and memory allocation is widely considered to be either a solved problem or …
Trace-driven memory simulation: A survey
As the gap between processor and memory speeds continues to widen, methods for
evaluating memory system designs before they are implemented in hardware are becoming …
evaluating memory system designs before they are implemented in hardware are becoming …
{MICA}: A holistic approach to fast {In-Memory}{Key-Value} storage
MICA is a scalable in-memory key-value store that handles 65.6 to 76.9 million key-value
operations per second using a single general-purpose multi-core system. MICA is over 4 …
operations per second using a single general-purpose multi-core system. MICA is over 4 …
Roofline: an insightful visual performance model for multicore architectures
Roofline: An insightful Visual Performance model for multicore Architectures Page 1 APriL 2009
| voL. 52 | no. 4 | communicAtionS of the Acm 65 conVentional WiSdom in computer architecture …
| voL. 52 | no. 4 | communicAtionS of the Acm 65 conVentional WiSdom in computer architecture …
[書籍][B] Parallel computer architecture: a hardware/software approach
The most exciting development in parallel computer architecture is the convergence of
traditionally disparate approaches on a common machine structure. This book explains the …
traditionally disparate approaches on a common machine structure. This book explains the …
On micro-kernel construction
J Liedtke - ACM SIGOPS Operating Systems Review, 1995 - dl.acm.org
Abstract Jochen Liedtke GMD—German National Research Center for Information
Technology* jochen. liedtke@ gmd. de From a software-technology point of view, the p …
Technology* jochen. liedtke@ gmd. de From a software-technology point of view, the p …
Why on-chip cache coherence is here to stay
Why on-chip cache coherence is here to stay Page 1 78 CommuniCations oF the aCm | juLy 2012
| voL. 55 | no. 7 contributed articles shAred MeMorY is the dominant low-level communication …
| voL. 55 | no. 7 contributed articles shAred MeMorY is the dominant low-level communication …
A case for two-way skewed-associative caches
A Seznec - ACM SIGARCH computer architecture news, 1993 - dl.acm.org
We introduce a new organization for multi-bank ca ch es: the skewed-associative cache. A
two-way skewed-associative cache has the same hardware complexity as a two-way set …
two-way skewed-associative cache has the same hardware complexity as a two-way set …
Efficient {MRC} construction with {SHARDS}
Reuse-distance analysis is a powerful technique for characterizing temporal locality of
workloads, often visualized with miss ratio curves (MRCs). Unfortunately, even the most …
workloads, often visualized with miss ratio curves (MRCs). Unfortunately, even the most …
Page placement algorithms for large real-indexed caches
RE Kessler, MD Hill - ACM Transactions on Computer Systems (TOCS), 1992 - dl.acm.org
When a computer system supports both paged virtual memory and large real-indexed
caches, cache performance depends in part on the main memory page placement. To date …
caches, cache performance depends in part on the main memory page placement. To date …