An evident challenge ahead for the integrated circuit (IC) industry is the investigation and
development of methods to reduce the design complexity ensuing from growing process …

To speed up the FPGA placement and routing closure, we propose a novel approach to
predict the routing congestion map for large-scale FPGA designs at the placement stage …

Due to sensitive layout-dependent effects and varied performance metrics, analog routing
automation for performance-driven layout synthesis is difficult to generalize. Existing …

The breakdown performance is a critical metric for power device design. This paper explores
the feasibility of efficiently predicting the breakdown performance of silicon on insulator (SOI) …

As the semiconductor manufacturing process is moving towards the 3 nm node, there is a
crucial need to reduce the edge placement error (EPE) to ensure proper functioning of the …

Electromigration (EM) is a major failure effect for on-chip power grid networks of deep
submicron VLSI circuits. EM degradation of metal grid lines can lead to excessive voltage …

In this paper, we propose a novel transient full-chip thermal map estimation method for multi-
core commercial CPU based on the data-driven generative adversarial learning method. We …

VLSI layout patterns provide critic resources in various design for manufacturability
researches, from early technology node development to back-end design and sign-off flows …

Electromigration (EM) analysis for complicated interconnects requires the solving of partial
differential equations, which is expensive. In this paper, we propose a fast transient …

There is substantial interest in the use of machine learning (ML)-based techniques
throughout the electronic computer-aided design (CAD) flow, particularly those based on …