A survey on multithreading alternatives for soft error fault tolerance

I Oz, S Arslan - ACM Computing Surveys (CSUR), 2019 - dl.acm.org
Smaller transistor sizes and reduction in voltage levels in modern microprocessors induce
higher soft error rates. This trend makes reliability a primary design constraint for computer …

An optimized weighted average makespan in fault-tolerant heterogeneous MPSoCs

H Youness, A Omar, M Moness - IEEE Transactions on Parallel …, 2021 - ieeexplore.ieee.org
The multiprocessor system on chips (MPSoCs) are considered today the core of most
modern systems. Most of the applications of these heterogeneous MPSoCs include critical …

Survey and future directions of fault-tolerant distributed computing on board spacecraft

M Fayyaz, T Vladimirova - Advances in Space Research, 2016 - Elsevier
Current and future space missions demand highly reliable on-board computing systems,
which are capable of carrying out high-performance data processing. At present, no single …

Cost-effective safety and fault localization using distributed temporal redundancy

BH Meyer, BH Calhoun, J Lach, K Skadron - Proceedings of the 14th …, 2011 - dl.acm.org
Cost pressure is driving vendors of safety-critical systems to integrate previously distributed
systems. One natural approach we have previous introduced is On-Demand Redundancy …

Energy-efficient fault tolerance in chip multiprocessors using critical value forwarding

P Subramanyan, V Singh, KK Saluja… - 2010 IEEE/IFIP …, 2010 - ieeexplore.ieee.org
Relentless CMOS scaling coupled with lower design tolerances is making ICs increasingly
susceptible to wear-out related permanent faults and transient faults, necessitating on-chip …

[HTML][HTML] Adaptive Switching Redundant-Mode Multi-Core System for Photovoltaic Power Generation

L Liu, X Zhang, J Zhou, K Niu, Z Guo, Y Zhao, M Zhang - Sensors, 2024 - mdpi.com
As maximum power point tracking (MPPT) algorithms have developed towards multi-task
intelligent computing, processors in photovoltaic power generation control systems must be …

Demystifying automotive safety and security for semiconductor developer

V Prasanth, D Foley, S Ravi - 2017 IEEE International Test …, 2017 - ieeexplore.ieee.org
Advances in both semiconductor and automotive industry are today enabling the next
generation of vehicles with significant electronics content than ever before. Consumers can …

Remo: Redundant execution with minimum area, power, performance overhead fault tolerant architecture

S Gopalakrishnan, V Singh - … on On-Line Testing and Robust …, 2016 - ieeexplore.ieee.org
Relentless scaling in CMOS fabrication technology has made contemporary integrated
circuits continue to evolve and grow in functionality with high clock frequencies and …

Thread-level redundancy fault tolerant CMP based on relaxed input replication

J Yu, D Jian, Z Wu, H Liu - 2011 6th international conference on …, 2011 - ieeexplore.ieee.org
To obtain the benefit of aggressive CMOS scaling, chip multiprocessors (CMP) has the
tendency of integrating more processors on one chip. However, the increase of cores and …

[PDF][PDF] Architectural framework for dynamically adaptable multiprocessors regarding aging, fault tolerance, performance and power consumption

A Simevski - 2014 - opus4.kobv.de
Despite the numerous benefits that Integrated Circuit (IC) technology downscaling brings, it
also introduces many challenges. First of all, IC dependability is lowering: both lifetime …