A novel test pattern generation method for multiple dc and ac faults is presented. The fault
models considered include line stuck-at, bridging, transition, and transistor stuck-open faults …

Abstract Detecting defects in Delay-Insensitive Circuits (DIC), particularly for clockless
asynchronous circuits, poses a major challenge. Traditional testing methods are complex …

In this paper, we analyse the impact of voltage, temperature and body-biasing on the
detection of resistive short defects for low-VT (LVT) and regular-VT (RVT) configurations of a …

Advances in integrated circuit process technology have led to new defect mechanisms, and
weak resistive defects in standard cells have received attention in addition to traditional …

This paper presents an in-depth analysis of the impact of body-biasing, supply voltage, and
temperature on the detection of resistive short defects in FDSOI technology. Three types of …

This paper presents a comprehensive study towards the identification and quantification of
the detectability improvement of resistive open and short defects, brought by specific supply …

The present paper evidences the existence of a sensitivity threshold of the triple modular
redundancy (TMR) structure combined with quasi delay insensitive (QDI) logic style …

Bridge defects are an important manufacturing defect that may escape test causing reliability
issues. It has been shown that in nanometer regime, process variations pose important …

This paper deals with the analysis of the impact of process variations on the detection of
resistive short defects, in the context of a logic-based test. Two types of short defects are …

A novel test pattern generation flow for both DC and AC faults is presented. All faults to be
processed are transformed into stuck-at faults with some constraints in a proposed two …