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A 0.6-V 38-nW 9.4-ENOB 20-kS/s SAR ADC in 0.18- CMOS for Medical Implant Devices
This paper presents a 10-bit ultra-low power successive approximation register (SAR)
analog-to-digital converter (ADC) for implantable medical devices. To achieve the nanowatt …
analog-to-digital converter (ADC) for implantable medical devices. To achieve the nanowatt …
A 12-bit 10 MS/s SAR ADC with high linearity and energy-efficient switching
S Liu, Y Shen, Z Zhu - … Transactions on Circuits and Systems I …, 2016 - ieeexplore.ieee.org
A 12-bit 10 MS/s SAR ADC with enhanced linearity and energy efficiency is presented in this
paper. A novel switching scheme (COSS) is proposed to reduce the power consumption and …
paper. A novel switching scheme (COSS) is proposed to reduce the power consumption and …
A 6-to-10-Bit 0.5 V-to-0.9 V Reconfigurable 2 MS/s Power Scalable SAR ADC in 0.18 CMOS
An asynchronous successive approximation register (SAR) analog-to-digital converter
(ADC) for sensor applications is presented. High linear and power efficient switching …
(ADC) for sensor applications is presented. High linear and power efficient switching …
A reconfigurable 10-to-12-b 80-to-20-MS/s bandwidth scalable SAR ADC
An asynchronous successive approximation register analog-to-digital converter (ADC) for
wideband multi-standard systems is presented. The ADC can be configured as an 80-MS/s …
wideband multi-standard systems is presented. The ADC can be configured as an 80-MS/s …
An energy efficient symmetrical DAC switching scheme for single-ended SAR ADCs with zero reset energy and a 3-stage common-mode insensitive regenerative …
H Pahlavanzadeh, MA Karami - AEU-International Journal of Electronics …, 2022 - Elsevier
A state-of-the-art energy-efficient digital-to-analog converter (DAC) switching scheme
suitable for single-ended successive approximation register (SAR) analog-to-digital …
suitable for single-ended successive approximation register (SAR) analog-to-digital …
A 6.94-fJ/conversion-step 12-bit 100-MS/s asynchronous SAR ADC exploiting split-CDAC in 65-nm CMOS
This paper presents a 12-bit 100-MS/s asynchronous successive approximation register
(SAR) analog-to-digital converter (ADC) for low-power wireless and imaging systems. A split …
(SAR) analog-to-digital converter (ADC) for low-power wireless and imaging systems. A split …
60-dB SNDR 100-MS/s SAR ADCs with threshold reconfigurable reference error calibration
This paper presents a reference error calibration scheme for successive approximation
register (SAR) analog-to-digital converters (ADCs) verified with two prototypes. Such a …
register (SAR) analog-to-digital converters (ADCs) verified with two prototypes. Such a …
An ultra-low power 10-bit, 50 MSps SAR ADC for multi-channel readout ASICs
M Firlej, T Fiutowski, M Idzik, S Kulis… - Journal of …, 2023 - iopscience.iop.org
The design and measurement results of a fast, ultra-low power, small area 10-bit SAR ADC,
developed for multi-channel readout systems, in particular for applications in particle physics …
developed for multi-channel readout systems, in particular for applications in particle physics …
Design of a memristor-based digital to analog converter (DAC)
A memristor element has been highlighted in recent years and has been applied to several
applications. In this work, a memristor-based digital to analog converter (DAC) was …
applications. In this work, a memristor-based digital to analog converter (DAC) was …
An 11b 450 MS/s three-way time-interleaved subranging pipelined-SAR ADC in 65 nm CMOS
Y Zhu, CH Chan, U Seng-Pan… - IEEE Journal of Solid …, 2016 - ieeexplore.ieee.org
This paper presents an 11 bit 450 MS/s three-way time-interleaved (TI) subranging pipelined-
successive approximation register (SAR) analog-to-digital converter (ADC). The proposed …
successive approximation register (SAR) analog-to-digital converter (ADC). The proposed …