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System, method, and computer program product for improving memory systems
MS Smith - US Patent 9,432,298, 2016 - Google Patents
H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid
state devices; Multistep manufacturing processes thereof the devices being of types …
state devices; Multistep manufacturing processes thereof the devices being of types …
A survey of techniques for modeling and improving reliability of computing systems
Recent trends of aggressive technology scaling have greatly exacerbated the occurrences
and impact of faults in computing systems. This has madereliability'a first-order design …
and impact of faults in computing systems. This has madereliability'a first-order design …
An architecture for fault-tolerant computation with stochastic logic
Mounting concerns over variability, defects, and noise motivate a new approach for digital
circuitry: stochastic logic, that is to say, logic that operates on probabilistic signals and so …
circuitry: stochastic logic, that is to say, logic that operates on probabilistic signals and so …
Shoestring: Probabilistic soft error reliability on the cheap
Aggressive technology scaling provides designers with an ever increasing budget of
cheaper and faster transistors. Unfortunately, this trend is accompanied by a decline in …
cheaper and faster transistors. Unfortunately, this trend is accompanied by a decline in …
Trading off cache capacity for reliability to enable low voltage operation
One of the most effective techniques to reduce a processor's power consumption is to
reduce supply voltage. However, reducing voltage in the context of manufacturing-induced …
reduce supply voltage. However, reducing voltage in the context of manufacturing-induced …
Reducing cache power with low-cost, multi-bit error-correcting codes
Technology advancements have enabled the integration of large on-die embedded DRAM
(eDRAM) caches. eDRAM is significantly denser than traditional SRAMs, but must be …
(eDRAM) caches. eDRAM is significantly denser than traditional SRAMs, but must be …
Energy-efficient cache design using variable-strength error-correcting codes
Voltage scaling is one of the most effective mechanisms to improve microprocessors' energy
efficiency. However, processors cannot operate reliably below a minimum voltage, Vccmin …
efficiency. However, processors cannot operate reliably below a minimum voltage, Vccmin …
Improving cache lifetime reliability at ultra-low voltages
Voltage scaling is one of the most effective mechanisms to reduce microprocessor power
consumption. However, the increased severity of manufacturing-induced parameter …
consumption. However, the increased severity of manufacturing-induced parameter …
[HTML][HTML] Open-source IP cores for space: A processor-level perspective on soft errors in the RISC-V era
This paper discusses principles and techniques to evaluate processors for dependable
computing in space applications. The focus is on soft errors, which dominate the failure rate …
computing in space applications. The focus is on soft errors, which dominate the failure rate …
Memory mapped ECC: Low-cost error protection for last level caches
This paper presents a novel technique, Memory Mapped ECC, which reduces the cost of
providing error correction for SRAM caches. It is important to limit such overheads as …
providing error correction for SRAM caches. It is important to limit such overheads as …