System, method, and computer program product for improving memory systems

MS Smith - US Patent 9,432,298, 2016 - Google Patents
H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid
state devices; Multistep manufacturing processes thereof the devices being of types …

A survey of techniques for modeling and improving reliability of computing systems

S Mittal, JS Vetter - IEEE Transactions on Parallel and …, 2015 - ieeexplore.ieee.org
Recent trends of aggressive technology scaling have greatly exacerbated the occurrences
and impact of faults in computing systems. This has madereliability'a first-order design …

An architecture for fault-tolerant computation with stochastic logic

W Qian, X Li, MD Riedel, K Bazargan… - IEEE transactions on …, 2010 - ieeexplore.ieee.org
Mounting concerns over variability, defects, and noise motivate a new approach for digital
circuitry: stochastic logic, that is to say, logic that operates on probabilistic signals and so …

Shoestring: Probabilistic soft error reliability on the cheap

S Feng, S Gupta, A Ansari, S Mahlke - ACM SIGARCH Computer …, 2010 - dl.acm.org
Aggressive technology scaling provides designers with an ever increasing budget of
cheaper and faster transistors. Unfortunately, this trend is accompanied by a decline in …

Trading off cache capacity for reliability to enable low voltage operation

C Wilkerson, H Gao, AR Alameldeen, Z Chishti… - ACM SIGARCH …, 2008 - dl.acm.org
One of the most effective techniques to reduce a processor's power consumption is to
reduce supply voltage. However, reducing voltage in the context of manufacturing-induced …

Reducing cache power with low-cost, multi-bit error-correcting codes

C Wilkerson, AR Alameldeen, Z Chishti, W Wu… - Proceedings of the 37th …, 2010 - dl.acm.org
Technology advancements have enabled the integration of large on-die embedded DRAM
(eDRAM) caches. eDRAM is significantly denser than traditional SRAMs, but must be …

Energy-efficient cache design using variable-strength error-correcting codes

AR Alameldeen, I Wagner, Z Chishti, W Wu… - ACM SIGARCH …, 2011 - dl.acm.org
Voltage scaling is one of the most effective mechanisms to improve microprocessors' energy
efficiency. However, processors cannot operate reliably below a minimum voltage, Vccmin …

Improving cache lifetime reliability at ultra-low voltages

Z Chishti, AR Alameldeen, C Wilkerson, W Wu… - Proceedings of the 42nd …, 2009 - dl.acm.org
Voltage scaling is one of the most effective mechanisms to reduce microprocessor power
consumption. However, the increased severity of manufacturing-induced parameter …

[HTML][HTML] Open-source IP cores for space: A processor-level perspective on soft errors in the RISC-V era

S Di Mascio, A Menicucci, E Gill, G Furano… - Computer Science …, 2021 - Elsevier
This paper discusses principles and techniques to evaluate processors for dependable
computing in space applications. The focus is on soft errors, which dominate the failure rate …

Memory mapped ECC: Low-cost error protection for last level caches

DH Yoon, M Erez - Proceedings of the 36th annual international …, 2009 - dl.acm.org
This paper presents a novel technique, Memory Mapped ECC, which reduces the cost of
providing error correction for SRAM caches. It is important to limit such overheads as …