[BOOK][B] Interconnection networks

J Duato, S Yalamanchili, L Ni - 2002 - books.google.com
The performance of most digital systems today is limited by their communication or
interconnection, not by their logic or memory. As designers strive to make more efficient use …

Dynamic voltage scaling with links for power optimization of interconnection networks

L Shang, LS Peh, NK Jha - The Ninth International Symposium …, 2003 - ieeexplore.ieee.org
Originally developed to connect processors and memories in multicomputers, prior research
and design of interconnection networks have focused largely on performance. As these …

Enhanced hypercubes

NF Tzeng, S Wei - IEEE Transactions on Computers, 1991 - computer.org
A hypercube with extra connections added between pairs of nodes through otherwise
unused links is investigated. The extra connections are made in a way that maximizes the …

Hierarchical cubic networks

K Ghose, KR Desai - IEEE Transactions on Parallel and …, 1995 - ieeexplore.ieee.org
We introduce a new interconnection network for large-scale distributed memory
multiprocessors called the hierarchical cubic network (HCN). We establish that the number …

Performance of multiprocessor interconnection networks

LN Bhuyan, Q Yang, DP Agrawal - Computer, 1989 - ieeexplore.ieee.org
A tutorial is provided on the performance evaluation of multiprocessor interconnection
networks, to guide system designers in their design process. A classification of …

[BOOK][B] Analysis of queueing networks with blocking

S Balsamo, V de Nitto Personé, R Onvural - 2001 - books.google.com
Queueing network models have been widely applied as a powerful tool for modelling,
performance evaluation, and prediction of discrete flow systems, such as computer systems …

Optimal distance networks of low degree for parallel computers

R Beivide, E Herrada, JL Balcazar… - IEEE Transactions on …, 1991 - computer.org
The authors introduce and study a family of interconnection schemes, the Midimew
networks, based on circulant graphs of degree 4. A family of such circulants is determined …

Exploring the design space of self-regulating power-aware on/off interconnection networks

V Soteriou, LS Peh - IEEE Transactions on Parallel and …, 2007 - ieeexplore.ieee.org
With power consumption becoming increasingly critical in interconnected systems, power-
aware networks become part-and-parcel of many single-chip and multichip systems. As …

Design-space exploration of power-aware on/off interconnection networks

V Soteriou, LS Peh - … Conference on Computer Design: VLSI in …, 2004 - ieeexplore.ieee.org
With power a major limiting factor in the design of scalable interconnected systems, power-
aware networks become inherent components of single-chip and multi-chip systems. As …

Method and apparatus for deadlock-free routing around an unusable routing component in an N-dimensional network

PR Pierce, LC Ernst, DS Dunning - US Patent 5,898,826, 1999 - Google Patents
A method and apparatus for deadlock-free routing around an unusable routing component
in a network reroutes paths between source and destination nodes by initially identifying an …