A ReRAM-based nonvolatile flip-flop with self-write-termination scheme for frequent-off fast-wake-up nonvolatile processors
Nonvolatile flip-flops (nvFFs) enable frequent-off processors to achieve fast power-off and
wake-up time while maintaining critical local computing states through parallel data …
wake-up time while maintaining critical local computing states through parallel data …
Segment and conflict aware page allocation and migration in DRAM-PCM hybrid main memory
Phase change memory (PCM), given its nonvolatility, potential high density, and low standby
power, is a promising candidate to be used as main memory in next generation computer …
power, is a promising candidate to be used as main memory in next generation computer …
Towards LDPC read performance of 3D flash memories with layer-induced error characteristics
3D flash memories have been widely developed to further increase the storage capacity of
SSDs by vertically stacking multiple layers. However, this special physical structure brings …
SSDs by vertically stacking multiple layers. However, this special physical structure brings …
Preserving smart sink-location privacy with delay guaranteed routing scheme for WSNs
A Semi Random Circle routing for mobile Sink joint Ray Routing for data (SRCRR) scheme
is proposed for preserving sink-location privacy with a delay guaranteed. In the SRCRR …
is proposed for preserving sink-location privacy with a delay guaranteed. In the SRCRR …
MaPHeA: A lightweight memory hierarchy-aware profile-guided heap allocation framework
Hardware performance monitoring units (PMUs) are a standard feature in modern
microprocessors for high-performance computing (HPC) and embedded systems, by …
microprocessors for high-performance computing (HPC) and embedded systems, by …
Energy-aware assignment and scheduling for hybrid main memory in embedded systems
In embedded systems, especially battery-driven mobile devices, energy is one of the most
critical performance metrics. Due to its high density and low standby power, phase change …
critical performance metrics. Due to its high density and low standby power, phase change …
Maphea: A framework for lightweight memory hierarchy-aware profile-guided heap allocation
Hardware performance monitoring units (PMUs) are a standard feature in modern
microprocessors, providing a rich set of microarchitectural event samplers. Recently …
microprocessors, providing a rich set of microarchitectural event samplers. Recently …
Persisting RB-Tree into NVM in a consistency perspective
Byte-addressable non-volatile memory (NVM) is going to reshape conventional computer
systems. With advantages of low latency, byte-addressability, and non-volatility, NVM can be …
systems. With advantages of low latency, byte-addressability, and non-volatility, NVM can be …
The design of an efficient swap mechanism for hybrid DRAM-NVM systems
Non-Volatile Memory (NVM) is becoming an attractive candidate to be the swap area in
embedded systems for its near-DRAM speed, low energy consumption, high density, and …
embedded systems for its near-DRAM speed, low energy consumption, high density, and …
Rebirth-FTL: Lifetime optimization via approximate storage for NAND flash memory
The lifetime of NAND flash cells significantly degrades with feature-size reductions and
multilevel cell technology. On the other hand, we have more and more approximate data …
multilevel cell technology. On the other hand, we have more and more approximate data …