Polynomial formal verification: Ensuring correctness under resource constraints
Recently, a lot of effort has been put into develo** formal verification approaches by both
academic and industrial research. In practice, these techniques often give satisfying results …
academic and industrial research. In practice, these techniques often give satisfying results …
Reinforcement learning for electronic design automation: Case studies and perspectives
Reinforcement learning (RL) algorithms have recently seen rapid advancement and
adoption in the field of electronic design automation (EDA) in both academia and industry. In …
adoption in the field of electronic design automation (EDA) in both academia and industry. In …
IR-Aware ECO Timing Optimization Using Reinforcement Learning
Engineering change orders (ECOs) in late stages make minimal design fixes to recover from
timing shifts due to excessive IR drops. This paper integrates IR-drop-aware timing analysis …
timing shifts due to excessive IR drops. This paper integrates IR-drop-aware timing analysis …
AI-Enhanced Codesign of Neuromorphic Circuits
Leading neuromorphic computer (NMC) platforms achieve energy efficiency and extreme
scalability by implementing simplified models of biological neurons. Future NMCs that rely …
scalability by implementing simplified models of biological neurons. Future NMCs that rely …
LSTM-Characterized Approach for Chip Floorplanning: Leveraging HyperGCN and DRQN
W Guan, X Tang, H Lu, J Tan, J Wang… - … on Computer-Aided …, 2024 - ieeexplore.ieee.org
In the field of very large-scale integration (VLSI) chip design, chip floorplanning plays a
crucial role as it directly influences key optimization objectives such as placement …
crucial role as it directly influences key optimization objectives such as placement …
RL-Legalizer: Reinforcement Learning-based Cell Priority Optimization in Mixed-Height Standard Cell Legalization
Cell legalization order has a substantial effect on the quality of modern VLSI designs, which
use mixed-height standard cells. In this paper, we propose a deep reinforcement learning …
use mixed-height standard cells. In this paper, we propose a deep reinforcement learning …
Enhancing K-Way Circuit Partitioning: A Deep Reinforcement Learning Methodology
Multiway circuit partitioning is a key combinatorial optimization problem that appears many
times throughout the Very Large Scale Integration (VLSI) design workflow. However, as VLSI …
times throughout the Very Large Scale Integration (VLSI) design workflow. However, as VLSI …
Efficient optimization methods for analog/mixed-signal integrated circuits via machine learning
AF Budak - 2023 - repositories.lib.utexas.edu
During the analog design process, a significant amount of human effort is spent on
optimizing circuit specifications by tuning the device parameters. Sizing device parameters …
optimizing circuit specifications by tuning the device parameters. Sizing device parameters …
IR-Aware ECO Timing Optimization Using Reinforcement Learning
Engineering change orders (ECOs) in late stages make minimal design fixes to recover from
timing shifts due to excessive IR drops. This paper integrates IR-drop-aware timing analysis …
timing shifts due to excessive IR drops. This paper integrates IR-drop-aware timing analysis …
AI-enhanced Codesign for Next-Generation Neuromorphic Circuits and Systems
This report details work that was completed to address the Fiscal Year 2022 Advanced
Science and Technology (AS&T) Laboratory Directed Research and Development (LDRD) …
Science and Technology (AS&T) Laboratory Directed Research and Development (LDRD) …