Multiplier Design using Machine Learning Alogorithms for Energy Efficiency Page 1 Journal
of VLSI circuits and systems, , ISSN 2582-1458 28 RESEARCH ARTICLE WWW.VLSIJOURNAL.COM …

This paper explores low-power and energy-efficient multi-bit Vedic Multiplier (VM)
architectures at a supply voltage as low as 0.6 V. Energy efficient architectures are a …

Since last few years, the tiny size of MOSFET, that is less than tens of nanometers, created
some operational problems such as increased gate-oxide leakage, amplified junction …

The electronics devices are facing a foremost drawback of standby leakage, which severely
impacting the electronics industry from the past few decades. As well as the need for cache …

A latch is used to store single bit information. It is a level triggered device. These are the
building blocks for sequential circuits. The basic working of D-Latch is that input data will be …

Barrel shifter architecture is well known for bit manipulation in a single clock cycle. Due to its
various operations and advantages, it is most likely used in the Arithmetic logic unit of every …

VLSI technology is essential for chip fabrication, and 3 to 8 decoder circuits are used in
electronic gadgets; consistency of design, small, fast, in this proposed circuit, 3 to 8 decoder …

In digital terminology, a device that compares two numbers which are represented in binary
format and determines whether one of the two inputs are lesser than or equal to or greater …

Abstract An innovative “Multiplexer based Thermometer to Binary code encoder” is
presented in this paper. This paper shows a relative decrease in the total count of …

Complex number arithmetic is pivotal in various applications, requiring the selection of an
efficient multiplier for high-performance computations. Fast Fourier transform (FFT)-based …