Real-time systems need time-predictable platforms to allow static analysis of the worst-case
execution time (WCET). Standard multi-core processors are optimized for the average case …

Industry 4.0 will only become a reality through the convergence of Operational and
Information Technologies (OT & IT), which use different computation and communication …

This paper presents an approach for hosting a representative avionic function on a
distributed-memory mul-ticore COTS architecture. This approach was developed in …

Current processors provide high average-case performance, as they are optimized for
general purpose computing. However, those optimizations often lead to a high worst-case …

The widespread proliferation of the Chip Multi-Processor (CMP) paradigm has cemented the
criticality of the on-chip interconnection fabric. The Network-on-Chip (NoC) is becoming …

We present MINOTAuR, a timing predictable open source RISC-V core based on the Ariane
core [28]. We first modify Ariane in order to make it timing predictable following the approach …

Acoustic-sensor-based soft error resilience is particularly promising, since it can verify the
absence of soft errors and eliminate silent data corruptions at a low hardware cost. However …

The construction of safety-critical real-time applications requires predictable computer
platforms that enable a safe and tight static analysis of those systems. The worst-case …

A good worst-case performance and the availability of high-quality bounds on the worst-
case execution time (WCET) of tasks are central for the construction of hard realtime …

Multi-core architectures pose many challenges in real-time systems, which arise from
contention between concurrent accesses to shared memory. Among the available memory …