Ultra-low noise defect probing instrument for defect spectroscopy of MOS transistors

M Waltl - IEEE Transactions on Device and Materials Reliability, 2020 - ieeexplore.ieee.org
It is commonly accepted that the performance and time-to-failure of modern semiconductor
transistors are seriously affected by single defects located in the insulator or at the insulator …

[HTML][HTML] Accelerating hydrogen sensing with Pd-MOS capacitors using active controls of trapped charge

N Solà-Peñafiel, G López-Rodriguez… - Sensors and Actuators B …, 2025 - Elsevier
Hydrogen monitoring with reliable, fast and cheap sensors is crucial to fully exploit the
potential of this gas as an energy vector. One of the most appealing technologies for …

The mysterious bipolar bias temperature stress from the perspective of gate-sided hydrogen release

T Grasser, B Kaczer, B O'Sullivan… - 2020 IEEE …, 2020 - ieeexplore.ieee.org
While the bias temperature instability has provided many puzzles for more than half a
century, the observation that bipolar (+ V g/-V g) AC stress can lead to larger degradation …

[PDF][PDF] On the electrical stability of 2D material-based field-effect transistors

T Knobloch - TU Wien Vienna, Austria, 2022 - scholar.archive.org
Over the past decades, the continued scaling of transistors has reduced the energy
consumption for every switching event and has increased the computational power of …

Hot-Carrier Damage in N-Channel EDMOS Used in Single Photon Avalanche Diode Cell through Quasi-Static Modeling

A Bravaix, H Pitard, X Federspiel, F Cacho - Micromachines, 2024 - mdpi.com
A single photon avalanche diode (SPAD) cell using N-channel extended-drain metal oxide
semiconductor (N-EDMOS) is tested for its hot-carrier damage (HCD) resistance. The …

Charge trap** and variability in CMOS technologies at cryogenic temperatures

JD Michl - 2022 - repositum.tuwien.at
CMOS technology operated at cryogenic temperatures is essential in various fields such as
quantum computing (QC), where it serves as a classical control interface for qubits operating …

Physical origin of the permanent components of the positive charge buildup resulting from NBTI/PBTI stress in nMOS/pMOS transistors

F Palumbo, M Klebanov, G Monreal… - … Symposium on the …, 2022 - ieeexplore.ieee.org
It is well established that the bias temperature instability (BTI) mechanism alters the Vth
distribution with reliability implications to balanced analog circuits. This paper presents a …

Reliability limiting defects in MOS gate oxides: Mechanisms and modeling implications

DM Fleetwood - 2019 IEEE International Reliability Physics …, 2019 - ieeexplore.ieee.org
Oxygen vacancies in SiO2 and dangling silicon bonds at the Si/SiOΣ2 interface are the most
significant gate-dielectric defects that limit the performance, reliability, and radiation …

Stability and reliability performance of double gate junctionless transistor (DG-JLT) 6T SRAM

N Garg, Y Pratap, S Kabra - 2021 International Conference on …, 2021 - ieeexplore.ieee.org
This work presents the impact of interface trap charges present at Si/SiO_2 interface on
I_ON/I_OFF ratio of double gate junctionless transistor (DG-JLT). DG-JLT is used to …

CV stretch-out correction after bias temperature stress: Work-function dependence of donor-/acceptor-like traps, fixed charges, and fast states

T Grasser, B O'Sullivan, B Kaczer… - 2021 IEEE …, 2021 - ieeexplore.ieee.org
Capacitance-voltage (CV) measurements on MOS structures are inherently difficult to
analyze due to the socalled stretch-out, which results from defects becoming charged during …