At each advanced technology node, it is crucial to characterize and understand the
mechanisms affecting performance and reliability. Scaling for all nodes prior to the 5-nm …

FinFET, with narrow silicon fin, and high k/metal gate stacked combined with SOI technology
brings benefits to radiation effects. Single event transient (SET) of SOI FinFET at 14 nm …

Scaling trends in the alpha-particle and neutron induced SRAM SER shows an increase in
the per-bit SER and percent multi-cell upsets at the 5-nm FinFET process compared to the 7 …

Soft error rates (SER) are characterized for the 5-nm bulk FinFET D flip-flops for alpha
particles, thermal neutrons, and high-energy neutrons as a function of supply voltage. At …

Single-event (SE) performance of a variety of radiation-hardened by design (RHBD) flip-flop
(FF) circuits is evaluated at the 7-and 5-nm bulk FinFET nodes. For a given RHBD …

Comparative modeling of induced charge in FinFET and MOSFET structures is performed. A
comparative analysis of the influence of various mechanisms on the occurrence of a current …

The impact of spacer on the single event response of SOI FinFET at 14 nm technology node
is investigated. Based on the device TCAD model, well-calibrated by the experimental data …

The Aerospace Corporation performed total ionizing dose (TID) and proton testing on the
AMD Ryzen 3200G processor. The Ryzen processor is a system on chip that contains a 4 …

With the scaling of fabrication processes, there is an increased cost per silicon area to
fabricate at the latest technology nodes. To optimize the cost of silicon area, the industry is …

With modern integrated circuits (ICs) operating at the GHz range of operation, the single-
event (SE) cross-section of an average logic circuit feeding data into a conventional latch …