New structure transistors for advanced technology node CMOS ICs

Q Zhang, Y Zhang, Y Luo, H Yin - National Science Review, 2024 - academic.oup.com
Over recent decades, advancements in complementary metal-oxide-semiconductor
integrated circuits (ICs) have mainly relied on structural innovations in transistors. From …

Toward attojoule switching energy in logic transistors

S Datta, W Chakraborty, M Radosavljevic - Science, 2022 - science.org
Advances in the theory of semiconductors in the 1930s in addition to the purification of
germanium and silicon crystals in the 1940s enabled the point-contact junction transistor in …

Tunnel field-effect transistors: Prospects and challenges

UE Avci, DH Morris, IA Young - IEEE Journal of the Electron …, 2015 - ieeexplore.ieee.org
The tunnel field-effect transistor (TFET) is considered a future transistor option due to its
steep-slope prospects and the resulting advantages in operating at low supply voltage (V …

Interfacial charge analysis of heterogeneous gate dielectric-gate all around-tunnel FET for improved device reliability

J Madan, R Chaujar - IEEE Transactions on Device and …, 2016 - ieeexplore.ieee.org
In this paper, we have investigated device reliability by studying the impact of interface traps,
both donor (positive interface charges) and acceptor (negative interface charges), present at …

Trap assisted tunneling and its effect on subthreshold swing of tunnel FETs

RN Sajjad, W Chern, JL Hoyt… - IEEE Transactions on …, 2016 - ieeexplore.ieee.org
We provide a detailed study of the oxide-semiconductor interface trap assisted tunneling
(TAT) mechanism in tunnel FETs to show how it contributes a major leakage current path …

Controlling the drain side tunneling width to reduce ambipolar current in tunnel FETs using heterodielectric BOX

S Sahay, MJ Kumar - IEEE transactions on electron devices, 2015 - ieeexplore.ieee.org
In this brief, we demonstrate using 2-D simulations that the use of a heterodielectric BOX
(HDB) above a highly doped ground plane can control the tunneling width at the channel …

DC and RF/analog performances of split source horizontal pocket and hetero stack TFETs considering interface trap charges: a simulation study

S Tiwari, R Saha - Microelectronics Reliability, 2022 - Elsevier
This work investigates the impact of different types of interface trap charges (ITCs) on
electrical parameters of split source horizontal pocket Z shape TFET (ZHP-TFET) and Hetero …

Numerical Simulation of N+ Source Pocket PIN-GAA-Tunnel FET: Impact of Interface Trap Charges and Temperature

J Madan, R Chaujar - IEEE Transactions on Electron Devices, 2017 - ieeexplore.ieee.org
This paper investigates the reliability of PINgate-all-around (GAA)-tunnel field-effect
transistor (TFET) with N±source pocket. The reliability of the PNIN-GAA-TFET is examined …

Trap and self-heating effect based reliability analysis to reveal early aging effect in nanosheet FET

S Rathore, RK Jaisawal, PN Kondekar, N Bagga - Solid-State Electronics, 2023 - Elsevier
The reliability of the CMOS devices is severely affected due to the presence of interface (S
i/S i O 2) trap charges and self-heating effect (SHE). In this paper, we investigated the trap …

Interfacial trap charge and self-heating effect based reliability analysis of a Dual-Drain Vertical Tunnel FET

D Das, CK Pandey - Microelectronics Reliability, 2023 - Elsevier
This manuscript exclusively addresses the reliability concern of a double-drain vertical TFET
(DD-VTFET) by analysing the influence of interface trap charges and variation in ambient …