57 ABSTRACT AP-channel single-poly non-volatile memory cell having P+ source and P+
drain regions and a channel extending ther ebetween is formed in an N-type well. An …

(57) ABSTRACT A memory array (10) is provided with a plurality of Flash EEPROM memory
cells (24) that are fabricated with a single level poly process. Each of the transistor cells (24) …

57 ABSTRACT A read-only memory device is provided which comprises an array of read-
only memory cells arranged in rows and columns. An additional row or column of flat, Single …

In an embodiment of the invention, a memory cell arrange ment includes a Substrate and at
least one memory cell includ ing a charge storing memory cell structure and a select struc …

A method of fabricating an integrated circuit (272) having memory, logic, high voltage, and
high current functionality uses a modular implant process step (104) to form a drain …

Kraus, LLP (57) ABSTRACT To reduce cost of defect redundancy and trimming in a
semiconductor integrated circuit having multiple layer wir ings and copper wirings, an …

4,162.504 4,185.319 4,209,849 4,258,378 4,266.283 4,274,012 4,288,863 4,297,719
4,305,083 4,314,265 4,317,110 4,332,077 4,336,603 4,355.375 4,366,556 4,375,085 …

State of the art nonvolatile memory devices are typically constructed by fabricating a field
effect transistor (FET) in a silicon substrate. The field effect transistor is capable of Storing …

4,047,163 9/1977 Choate et al....... 340/173 R Single polysilicon mask ROM processes.
Redundancy cells 4,250,570 2/1981 Tsang et al...... 265/200 are based upon a diffusion …

(57) ABSTRACT Related US Application Data A semiconductor integrated circuit device
having a bipolar 63 continuation of ser, No. 45,125 Apr 12, 1993, abandoned transistor and …