In order to mitigate the impact of the growing gap between CPU speed and main memory
performance, today's computer architectures implement hierarchical memory structures. The …

Over the last decade, we have seen a revolution in connectivity between computers, and a
resulting paradigm shift from centralized to highly distributed systems. With massive scale …

When dense matrix computations are too large to fit in cache, previous research proposes
tiling to reduce or eliminate capacity misses. This paper presents a new algorithm for …

Impulse is a new memory system architecture that adds two important features to a
traditional memory controller. First, Impulse supports application-specific optimizations …

This paper describes a general and robust loop transformation framework that enables
compilers to generate efficient code on complex loop nests. Despite two decades of prior …

Current data cache organizations fail to deliver high performance in scalar processors for
many vector applications. There are two main reasons for this loss of performance: the use …

With the ever-widening performance gap between processors and main memory, cache
memory, which is used to bridge this gap, is becoming more and more significant. Caches …

Compiler transformations can significantly improve data locality for many scientific programs.
In this paper, we show iterative solvers for partial differential equations (PDEs) in three …

The widening gap between memory and processor speed causes more and more programs
to shift from CPU-bounded to memory speed-bounded, even in the presence of multi-level …

Effective memory hierarchy utilization is critical to the performance of modern multiprocessor
architectures. We have developed the first compiler system that fully automatically …