Invisispec: Making speculative execution invisible in the cache hierarchy

M Yan, J Choi, D Skarlatos, A Morrison… - 2018 51st Annual …, 2018 - ieeexplore.ieee.org
Hardware speculation offers a major surface for micro-architectural covert and side channel
attacks. Unfortunately, defending against speculative execution attacks is challenging. The …

A" flight data recorder" for enabling full-system multiprocessor deterministic replay

M Xu, R Bodik, MD Hill - Proceedings of the 30th annual international …, 2003 - dl.acm.org
Debuggers have been proven indispensable in improving software reliability. Unfortunately,
on most real-life software, debuggers fail to deliver their most essential feature---a faithful …

Core fusion: accommodating software diversity in chip multiprocessors

E Ipek, M Kirman, N Kirman, JF Martinez - Proceedings of the 34th …, 2007 - dl.acm.org
This paper presents core fusion, a reconfigurable chip multiprocessor (CMP) architecture
where groups of fundamentally independent cores can dynamically morph into a larger …

Specshield: Shielding speculative data from microarchitectural covert channels

K Barber, A Bacha, L Zhou, Y Zhang… - 2019 28th …, 2019 - ieeexplore.ieee.org
Hardware security has recently re-surfaced as a first-order concern to the confidentiality
protections of computing systems. Meltdown and Spectre introduced a new class of …

A survey and taxonomy of on-chip monitoring of multicore systems-on-chip

G Kornaros, D Pnevmatikatos - ACM Transactions on Design Automation …, 2013 - dl.acm.org
Billion transistor systems-on-chip increasingly require dynamic management of their
hardware components and careful coordination of the tasks that they carry out. Diverse real …

Checkpoint processing and recovery: Towards scalable large instruction window processors

H Akkary, R Rajwar… - Proceedings. 36th Annual …, 2003 - ieeexplore.ieee.org
Large instruction window processors achieve high performance by exposing large amounts
of instruction level parallelism. However, accessing large hardware structures typically …

BulkSC: Bulk enforcement of sequential consistency

L Ceze, J Tuck, P Montesinos, J Torrellas - Proceedings of the 34th …, 2007 - dl.acm.org
While Sequential Consistency (SC) is the most intuitive memory consistency model and the
one most programmers likely assume, current multiprocessors do not support it. Instead …

GPU register file virtualization

H Jeon, GS Ravi, NS Kim, M Annavaram - Proceedings of the 48th …, 2015 - dl.acm.org
To support massive number of parallel thread contexts, Graphics Processing Units (GPUs)
use a huge register file, which is responsible for a large fraction of GPU's total power and …

Continual flow pipelines

ST Srinivasan, R Rajwar, H Akkary, A Gandhi… - ACM SIGARCH …, 2004 - dl.acm.org
Increased integration in the form of multiple processor cores on a single die, relatively
constant die sizes, shrinking power envelopes, and emerging applications create a new …

Utilizing dynamically coupled cores to form a resilient chip multiprocessor

C LaFrieda, E Ipek, JF Martinez… - 37th Annual IEEE/IFIP …, 2007 - ieeexplore.ieee.org
Aggressive CMOS scaling will make future chip multiprocessors (CMPs) increasingly
susceptible to transient faults, hard errors, manufacturing defects, and process variations …