Invisispec: Making speculative execution invisible in the cache hierarchy
Hardware speculation offers a major surface for micro-architectural covert and side channel
attacks. Unfortunately, defending against speculative execution attacks is challenging. The …
attacks. Unfortunately, defending against speculative execution attacks is challenging. The …
A" flight data recorder" for enabling full-system multiprocessor deterministic replay
Debuggers have been proven indispensable in improving software reliability. Unfortunately,
on most real-life software, debuggers fail to deliver their most essential feature---a faithful …
on most real-life software, debuggers fail to deliver their most essential feature---a faithful …
Core fusion: accommodating software diversity in chip multiprocessors
This paper presents core fusion, a reconfigurable chip multiprocessor (CMP) architecture
where groups of fundamentally independent cores can dynamically morph into a larger …
where groups of fundamentally independent cores can dynamically morph into a larger …
Specshield: Shielding speculative data from microarchitectural covert channels
Hardware security has recently re-surfaced as a first-order concern to the confidentiality
protections of computing systems. Meltdown and Spectre introduced a new class of …
protections of computing systems. Meltdown and Spectre introduced a new class of …
A survey and taxonomy of on-chip monitoring of multicore systems-on-chip
Billion transistor systems-on-chip increasingly require dynamic management of their
hardware components and careful coordination of the tasks that they carry out. Diverse real …
hardware components and careful coordination of the tasks that they carry out. Diverse real …
Checkpoint processing and recovery: Towards scalable large instruction window processors
Large instruction window processors achieve high performance by exposing large amounts
of instruction level parallelism. However, accessing large hardware structures typically …
of instruction level parallelism. However, accessing large hardware structures typically …
BulkSC: Bulk enforcement of sequential consistency
While Sequential Consistency (SC) is the most intuitive memory consistency model and the
one most programmers likely assume, current multiprocessors do not support it. Instead …
one most programmers likely assume, current multiprocessors do not support it. Instead …
GPU register file virtualization
To support massive number of parallel thread contexts, Graphics Processing Units (GPUs)
use a huge register file, which is responsible for a large fraction of GPU's total power and …
use a huge register file, which is responsible for a large fraction of GPU's total power and …
Continual flow pipelines
Increased integration in the form of multiple processor cores on a single die, relatively
constant die sizes, shrinking power envelopes, and emerging applications create a new …
constant die sizes, shrinking power envelopes, and emerging applications create a new …
Utilizing dynamically coupled cores to form a resilient chip multiprocessor
Aggressive CMOS scaling will make future chip multiprocessors (CMPs) increasingly
susceptible to transient faults, hard errors, manufacturing defects, and process variations …
susceptible to transient faults, hard errors, manufacturing defects, and process variations …