Prune+ PlumTree-Finding Eviction Sets at Scale

T Kessous, N Gilboa - 2024 IEEE Symposium on Security and Privacy …, 2024 - computer.org
Finding eviction sets for a large fraction of the cache is an essential preprocessing step for
Prime+ Probe based cache side-channel attacks. Previous work on this problem reduces it …

FlushTime: Towards Mitigating Flush-based Cache Attacks via Collaborating Flush Instructions and Timers on ARMv8-A

J Ge, F Zhang - Proceedings of the 2023 ACM Asia Conference on …, 2023 - dl.acm.org
ARMv8-A processors generally utilize optimization techniques such as multi-layer cache, out-
of-order execution and branch prediction to improve performance. These optimization …

One more set: Mitigating conflict-based cache side-channel attacks by extending cache set

Y Gu, M Tang, Q Wang, H Wang, H Ding - Journal of Systems Architecture, 2023 - Elsevier
Caches are vulnerable to side-channel attacks as a type of shared hardware resource. Most
existing defense methods can be categorized into two categories: partition and …

NVM-Flip: Non-Volatile-Memory BitFlips on the System Level

F Staudigl, JP Thoma, C Niesler, K Sturm… - Proceedings of the …, 2024 - dl.acm.org
Emerging non-volatile memories (NVMs), such as spin-torque transfer memory (STT-
RAM/MRAM)[36], phase-change random access memory (PCRAM)[14], or redox-based …

Basicblocker: Isa redesign to make spectre-immune cpus faster

JP Thoma, J Feldtkeller, M Krausz, T Güneysu… - Proceedings of the 24th …, 2021 - dl.acm.org
Recent research has revealed an ever-growing class of microarchitectural attacks that
exploit speculative execution, a standard feature in modern processors. Proposed and …

BackCache: Mitigating contention-based cache timing attacks by hiding cache line evictions

Q Wang, X Zhang, H Wang, Y Gu, M Tang - arxiv preprint arxiv …, 2023 - arxiv.org
Caches are used to reduce the speed differential between the CPU and memory to improve
the performance of modern processors. However, attackers can use contention-based cache …