Semiconductor on insulator structure comprising a plasma nitride layer and method of manufacture thereof

SJ Kweskin - US Patent 11,114,332, 2021 - Google Patents
US11114332B2 - Semiconductor on insulator structure comprising a plasma nitride layer and
method of manufacture thereof - Google Patents US11114332B2 - Semiconductor on insulator …

Surface acoustic wave (SAW) resonator having trap-rich region

SR Gilbert, RC Ruby - US Patent 10,541,667, 2020 - Google Patents
(57) ABSTRACT A surface acoustic wave (SAW) resonator device includes a semiconductor
substrate having a first surface and a second surface. The semiconductor substrate …

Encapsulated dies with enhanced thermal performance

TS Morris, D Jandzinski, S Parker, J Chadwick… - US Patent …, 2017 - Google Patents
The present disclosure relates to enhancing the thermal performance of encapsulated flip
chip dies. According to an exemplary process, a plurality of flip chip dies are attached on a …

RF harmonic distortion of CPW lines on HR-Si and trap-rich HR-Si substrates

CR Neve, JP Raskin - IEEE Transactions on Electron Devices, 2012 - ieeexplore.ieee.org
In this paper, the nonlinear behavior of coplanar waveguide (CPW) transmission lines
fabricated on Si and high-resistivity (HR) Si substrates is thoroughly investigated …

Method of manufacture for a silicon-on-plastic semiconductor device with interfacial adhesion layer

JC Costa - US Patent 9,812,350, 2017 - Google Patents
(57) ABSTRACT A semiconductor device and methods for manufacturing the same are
disclosed. The semiconductor device includes a polymer substrate and an interfacial layer …

Flip chip module with enhanced properties

JC Costa, TS Morris, JH Hammond… - US Patent …, 2018 - Google Patents
A flip chip module having at least one flip chip die is disclosed. The flip chip module includes
a carrier having a top surface with a first mold compound residing on the top surface. A first …

Silicon-on-plastic semiconductor device and method of making the same

JC Costa, DM Shuttleworth, MJ Antonell - US Patent 9,583,414, 2017 - Google Patents
(57) ABSTRACT A semiconductor device that does not produce nonlinearities attributed to a
high resistivity silicon handle interfaced with a dielectric region of a buried oxide (BOX) layer …

Method of manufacturing high resistivity SOI wafers with charge trap** layers based on terminated Si deposition

I Peidous, IKM Pellicano - US Patent 9,768,056, 2017 - Google Patents
US9768056B2 - Method of manufacturing high resistivity SOI wafers with charge trap** layers
based on terminated Si deposition - Google Patents US9768056B2 - Method of manufacturing …

RF SOI switch FET design and modeling tradeoffs for GSM applications

S Parthasarathy, A Trivedi, S Sirohi… - … Conference on VLSI …, 2010 - ieeexplore.ieee.org
A single-pole double-throw novel switch device in0. 18¹m SOI complementary metal-oxide
semiconductor (CMOS) process is developed for 0.9 Ghz wireless GSMsystems. The layout …

Method for manufacturing an integrated circuit package

JC Costa, G Maxim, DRW Leipold, B Scott - US Patent 10,085,352, 2018 - Google Patents
This disclosure relates to integrated circuit (IC) packages and methods of manufacturing the
same. In one method, a printed circuit board is provided with semiconductor die. The …