An area efficient vedic multiplier for FFT processor implementation using 4-2 compressor adder

S Dhanasekar - International Journal of Electronics, 2024 - Taylor & Francis
This article proposes a compact compressor adder of Vedic multiplication for an area-
efficient FFT architecture. A standard multi-radix-24, 22, 23 FFT with a single-path delay …

Area-power analysis of fft based digital beamforming for geo, meo, and leo scenarios

R Palisetty, G Eappen, JLG Rios… - 2022 IEEE 95th …, 2022 - ieeexplore.ieee.org
Satellite communication systems can provide seamless wireless coverage directly or
through complementary ground-terrestrial components and are projected to be incorporated …

Design of FFT processor using low power Vedic multiplier for wireless communication

C Padma, P Jagadamba, PR Reddy - Computers & Electrical Engineering, 2021 - Elsevier
Abstract Digital Signal Processing (DSP) is a very significant and active research area. High
throughput is a requirement for most wireless communication systems. The critical …

Low power pipelined FFT processor architecture on FPGA

SLM Hassan, N Sulaiman… - 2018 9th IEEE control and …, 2018 - ieeexplore.ieee.org
Fast Fourier Transform (FFT) processor is the hardware implementation for FFT algorithms
for Discrete Fourier Transform (DFT) which compute any signal in time domain to frequency …

Design and FPGA-based hardware implementation of NB-IoT physical uplink shared channel transmitter and physical downlink shared channel receiver

A Abostait, RM Tawfik, MS Darweesh, H Mostafa - Electronics, 2023 - mdpi.com
With the anticipated growth of the internet of things (IoT) market, many low-power wide-area
(LPWA) technologies have been introduced to connect a wide range of IoT devices with …

[PDF][PDF] VLSI implementation of variable bit rate OFDM transceiver system with multi-radix FFT/IFFT processor for wireless applications

D SUBRAMANIYAM, R JAYABALAN - Journal of Electrical …, 2018 - academia.edu
In this paper, a Variable Bit Rate 64 Subcarrier OFDM Transceiver system is implemented in
FPGA and the Modified Multi-radix 64 point FFT/IFFT blocks present in the OFDM design is …

[HTML][HTML] A pipelined FFT processor using an optimal hybrid rotation scheme for complex multiplication: design, FPGA implementation and analysis

HN Nguyen, SA Khan, CH Kim, JM Kim - Electronics, 2018 - mdpi.com
The fast Fourier transform (FFT) is the most prevalent algorithm for the spectral analysis of
acoustic emission signals acquired at ultra-high sampling rates to monitor the condition of …

Implementation of a 4-parallel 128-point radix-8 FFT processor via folding transformation

KH Viglianco, DR Garcia… - … Argentine Conference on …, 2023 - ieeexplore.ieee.org
This work describes the design and implementation of a 4-parallel 128-point pipelined
architecture for the fast Fourier transform (FFT) based on the radix-8 butterfly element using …

Synthesis and Time Analysis of FPGA‐Based DIT‐FFT Module for Efficient VLSI Signal Processing Applications

SK Panda, K Achyut, DC Panda - … Machine Learning Models …, 2023 - Wiley Online Library
Now is the era of high‐speed processors with reconfigurable architectures. The dedicated
architectures have a wide variety of applications in signal processing, image processing …

[PDF][PDF] Efficient cached 64 point FFT processor using floating point arithmetic for OFDM application

C Padma, P Jagadamba, RR Patil - Instrumentation, Mesure …, 2022 - researchgate.net
Accepted: 9 February 2022 Presently Fourth generation and other wireless systems are
focused area for the research and development in the communication field. Fast Fourier …