A thread scheduling mechanism is provided that flexibly enforces performance isolation of
multiple threads to alleviate the effect of anti-cooperative execution behavior with respect to …

A system and method can support efficient packet processing in a network environment. The
system can comprise a direct memory access (DMA) resources pool that comprises one or …

A hardware wake-and-go mechanism is provided for a data processing system. The wake-
and-go mechanism looks ahead in a thread for programming idioms that indicates that the …

A system and method can support dynamic provisioning in a network switch environment,
such as supporting virtualized switch classification tables in a network switch. The system …

Restricted instructions are prohibited from execution within a transaction. There are classes
of instructions that are restricted regardless of type of transaction: constrained or …

Methods, systems and computer program products for global address space management
are described herein. A System-On-a-Chip (SOC) unit configured for a global address space …

Program exception conditions cause a transaction to abort and typically result in an
interruption in which the operating system obtains control. A program interruption filtering …

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et al. 5,083,266 A 1/1992 Watanabe 5,161,227 A 11/1992 Dias et al. 5,202,988 A 4/1993 …

(54) METHOD FOR MAINTAINING ATOMICITY 6,678,772 B2 1/2004 McKenney OF
INSTRUCTION SEQUENCE TO ACCESSA 7,117,481 B1* 10/2006 Agesen et al …

WAKE-AND-GO lating a wake-and-go storage array with the target address. The operating
system places the thread in a sleep state. Responsive to detecting the event that modifies …