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High performance 2D transform hardware for future video coding
Future Video Coding (FVC) is a new international video compression standard offering
much better compression efficiency than previous video compression standards at the …
much better compression efficiency than previous video compression standards at the …
4K real-time HEVC decoder on an FPGA
With the popularization of a quad high-definition/4K video being dependent on the
availability of real-time High Efficiency Video Coding (HEVC) decoders, hardware …
availability of real-time High Efficiency Video Coding (HEVC) decoders, hardware …
A computation and energy reduction technique for HEVC discrete cosine transform
In this paper, a novel computation and energy reduction technique for High Efficiency Video
Coding (HEVC) Discrete Cosine Transform (DCT) for all Transform Unit (TU) sizes is …
Coding (HEVC) Discrete Cosine Transform (DCT) for all Transform Unit (TU) sizes is …
A combined deblocking filter and SAO hardware architecture for HEVC
W Shen, Y Fan, Y Bai, L Huang… - IEEE Transactions …, 2016 - ieeexplore.ieee.org
The latest video coding standard high-efficiency video coding (HEVC) provides 50%
improvement in coding efficiency compared to H. 264/AVC to meet the rising demands for …
improvement in coding efficiency compared to H. 264/AVC to meet the rising demands for …
A low energy HEVC inverse transform hardware
E Kalali, E Ozcan, OM Yalcinkaya… - IEEE Transactions on …, 2014 - ieeexplore.ieee.org
In this paper, a novel energy reduction technique for High Efficiency Video Coding (HEVC)
Inverse Discrete Cosine Transform (IDCT) and Inverse Discrete Sine Transform (IDST) for all …
Inverse Discrete Cosine Transform (IDCT) and Inverse Discrete Sine Transform (IDST) for all …
GHEVC: An efficient HEVC decoder for graphics processing units
The high compression efficiency that is provided by the high efficiency video coding (HEVC)
standard comes at the cost of a significant increase of the computational load at the decoder …
standard comes at the cost of a significant increase of the computational load at the decoder …
The VLSI architecture of a highly efficient deblocking filter for HEVC systems
PK Hsu, CA Shen - IEEE Transactions on Circuits and Systems …, 2016 - ieeexplore.ieee.org
This paper presents the VLSI architecture and hardware implementation of a highly efficient
deblocking filter (DBF) for High Efficiency Video Coding systems. In order to reduce the …
deblocking filter (DBF) for High Efficiency Video Coding systems. In order to reduce the …
A reconfigurable hardware architecture for fractional pixel interpolation in high efficiency video coding
We present a novel reconfigurable hardware architecture for interpolation filtering in high
efficient video coding that adapts to run-time changes of the number of interpolation filter …
efficient video coding that adapts to run-time changes of the number of interpolation filter …
Resource-aware architecture design and implementation of Hough transform for a real-time iris boundary detection system
HT Ngo, RN Rakvic, RP Broussard… - IEEE transactions on …, 2014 - ieeexplore.ieee.org
In this paper, a resource efficient architecture design for the circular Hough transform based
on Field Programmable Gate Array (FPGA) technology is presented. The circular Hough …
on Field Programmable Gate Array (FPGA) technology is presented. The circular Hough …
A fast integrated deblocking filter and sample-adaptive-offset parameter estimation architecture for HEVC
A Singhadia, M Minhazuddin, M Mamillapalli… - Microprocessors and …, 2021 - Elsevier
Low power hardware acceleration cores for integration into real-time High Efficiency Video
Coding (HEVC) codec for smartphones, tablets, camcorders, and televisions are in great …
Coding (HEVC) codec for smartphones, tablets, camcorders, and televisions are in great …