Single-electron transistor: review in perspective of theory, modelling, design and fabrication

R Patel, Y Agrawal, R Parekh - Microsystem Technologies, 2021 - Springer
Integrated circuit (IC) technology has grown tremendously over the last few decades. The
prime goal has been to achieve low-power and high-performance in logic and memory …

A Single Electron Transistor-Based Floating Point Multiplier Realization at Room Temperature Operation

S Banik, R Trivedi, A Kalavadiya, Y Agrawal… - … Technology Trends in …, 2022 - Springer
Floating point numbers provide more range as compared to the fixed point values. The
multiplier is one of the main blocks of a processor. For improved performance, there is a …

Design of Prominent Single-Precision 32-Bit Floating-Point Adder Using Single-Electron Transistor Operating at Room Temperature

A Sharma, R Dhavse, Y Agrawal, R Parekh - Advances in VLSI and …, 2021 - Springer
The floating-point (FP) addition is the most frequently used FP operation. Here we are using
single-electron transistor (SET) for floating-point addition. This research aims to implement a …

Design and implementation of quaternary summation circuit with single electron transistor and MOSFET

V Raut, P Dakhole - 2016 International Conference on …, 2016 - ieeexplore.ieee.org
This paper presents a novel approach for designing of quaternary logic SETMOS summation
circuit, hybrid circuits consisting of SET & MOSFET. Various gates based on hybrid structure …

Characteristics of Energy in the Coulomb Island of Single Electron Transistor

N Hussain, MA Hossain, N Mumenin… - 2022 International …, 2022 - ieeexplore.ieee.org
In the age of silicon technology consumption of low power is a primary challenge due to its
practical necessity. For meeting this criterion in design protocol, extensive usage of …

Design and Simulation of Single Electron Transistor Based High-Performance Computing System at Room Temperature

R Patel - 2021 - 14.139.122.115
" The VLSI technology has seamlessly grown over the years, that yields high-performance,
low-power and high-density devices. Over the several decades, the performance of existing …

Design and optimization of single electron transistor based 4-bit arithmetic and logic unit at room temperature operation

R Joshi, R Parekh, Y Agrawal - 2017 IEEE International …, 2017 - ieeexplore.ieee.org
Single electron transistor (SET) has been envisaged as a potential device to achieve high-
end performance in deep sub-micron technologies. The paper innovatively presents a 4-bit …

Design and implementation of binary and quaternary low power selective circuit using single electron transistor

V Raut, PK Dakhole - 2015 International Conference on …, 2015 - ieeexplore.ieee.org
This paper presents the performance analysis of single electron transistor (SET) low power
Arithmetic & Logical selective Unit. SET which is low power device is used to produce new …

[PDF][PDF] Comparative Analysis of Quaternary SETMOS Multiplexer

MV Raut, P Dakhole - academia.edu
This paper introduces the comparative analysis of binary logic with quaternary logic. As
quaternary logic build the circuits which are more compact and simple as compared with …

Design and Simulation of Hybrid SETMOS Operator Using Multiple Value Logic at 120 nm Technology

R Vaishali, PK Dakhole - Proceedings of the International Conference on …, 2017 - Springer
Motivation behind this paper is to bring new method for multi-feature compact designs with
low power requirement which is beyond the capacity of binary logic as well as use of only …