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C-PHY data-triggered edge generation with intrinsic half-rate operation
D Ying, SW Chou, Y Duan, A Dixit - US Patent 11,327,914, 2022 - Google Patents
Methods, apparatus, and systems for clock and data recovery in a C-PHY interface are
disclosed. A receiving device has a plurality of differential receivers and a recovery circuit …
disclosed. A receiving device has a plurality of differential receivers and a recovery circuit …
Semiconductor device
A semiconductor device including a comparison circuit configured to receive an input signal
having n signal levels, where n is a natural number equal to or greater than three, and …
having n signal levels, where n is a natural number equal to or greater than three, and …
Semiconductor device and memory system
KIM Kyoungho, C Kim, H Park… - US Patent 12,211,572, 2025 - Google Patents
A semiconductor device includes a multilevel receiver including a signal determiner
receiving a plurality of multilevel signals and outputting a result of mutual comparison of the …
receiving a plurality of multilevel signals and outputting a result of mutual comparison of the …