Hardware verification of modern electronic systems has been identified as a major
bottleneck due to the increasing complexity and time-to-market constraints. One of the major …

Gait recognition has gained increasing interest from researchers, but there is still no
standard evaluation method to compare the performance of different gait recognition …

Applying modern data mining in electronic design automation and test has become an area
of growing interest in recent years. This paper reviews some of the recent developments in …

The security of computer systems typically relies on a hardware root of trust. As
vulnerabilities in hardware can have severe implications on a system, there is a need for …

System-on-Chip (SoC) security is vital in designing trustworthy systems. Detecting and fixing
a vulnerability in the early stages is easier and cost-effective. Assertion-based verification is …

We present GoldMine, a methodology for generating assertions automatically in hardware.
Our method involves a combination of data mining and static analysis of the register transfer …

This article presents HARM, a tool to generate linear temporal logic (LTL) assertions starting
from a set of user-defined hints and the simulation traces of the design under verification …

Several approaches exist for specification mining of hardware designs. Most of them work at
RTL and they extract assertions in the form of temporal relations between Boolean variables …

(57) ABSTRACT A method of generating assertions for verification of a hard ware design
expressed at a register transfer level (RTL) includes running simulation traces through the …

We present HYBRO, an automatic methodology to generate high coverage input vectors for
Register Transfer Level (RTL) designs based on branch-coverage directed approach …