Variations in process parameters affect the operation of integrated circuits (ICs) and pose a
significant threat to the continued scaling of transistor dimensions. Such parameter …

In the last five decades, the number of transistors on a chip has increased exponentially in
accordance with the Moore's law, and the semiconductor industry has followed this law as …

A blueprint for an atomistic approach to introducing time-dependent variability into a circuit
simulator in a realistic manner is demonstrated. The approach is based on previously …

We present an aging analysis flow able to calculate the degraded circuit timing. To the best
of our knowledge it is the first approach on gate level so far capable of analyzing the impact …

Circuit reliability is affected by various fabrication-time and run-time effects. Fabrication-
induced process variation has significant impact on circuit performance and reliability …

Negative Bias Temperature Instability (NBTI), a PMOS aging phenomenon causing
significant loss on circuit performance and lifetime, has become a critical challenge for …

We review the literature for reliability-and process-variation aware VLSI design to find that
an exciting area of research/application is rapidly emerging as a core topic of IC design …

This paper evaluates the severity of negative bias temperature instability (NBTI) degradation
in two major circuit applications: random logic and memory array. For improved lifetime …

While negative bias temperature instability (NBTI) effects on logic gates are of major concern
for the reliability of digital circuits, they become even more critical when considering the …

Nanometer-scale circuits are fundamentally different from those built in their predecessor
technologies in that they are subject to a wide range of new effects that induce on-chip …