Chip-level power and thermal implications will continue to rule as one of the primary design
constraints and performance limiters. The gap between average and peak power actually …

Power density continues to increase exponentially with each new technology generation,
posing a major challenge for thermal management in modern processors. Much past work …

Previous proposals for power-aware thread-level parallelism on chip multiprocessors
(CMPs) mostly focus on multiprogrammed workloads. Nonetheless, parallel computation of …

This paper is motivated by three recent trends in computer design. First, chip multi-
processors (CMPs) with increasing numbers of CPU cores per chip are becoming common …

Previous studies have demonstrated the advantages of single-ISA heterogeneous multi-core
architectures for power and performance. However, none of those studies examined how to …

In this paper, we show how 3D stacking technology can be used to implement a simple, low-
power, high-performance chip multiprocessor suitable for throughput processing. Our …

This paper explores the multi-dimensional design space for chip multiprocessors, exploring
the inter-related variables of core count, pipeline depth, superscalar width, L2 cache size …

Future multicore processors will be heterogeneous, be increasingly less reliable, and
operate in dynamically changing operating conditions. Such environments will result in a …

Computing has recently reached an inflection point with the introduction of multi-core
processors. On-chip thread-level parallelism is doubling approximately every other year …

With technology advances, the number of cores integrated on a chip and their speed of
operation is increasing. This, in turn is leading to a significant increase in chip temperature …