Communication system with low power, DC-balanced serial link
WJ Dally, JW Poulton - US Patent 7,199,728, 2007 - Google Patents
103 circuit integrates codewords by integrating for a first interval with a positive polarity
within a particular symbol cell, and integrating for a second interval with a negative polarity …
within a particular symbol cell, and integrating for a second interval with a negative polarity …
Apparatus and method for controlling a master/slave system via master device synchronization
S Sidiropoulos - US Patent 6,839,393, 2005 - Google Patents
SUMMARY OF THE INVENTION A method of operating a master/slave System includes the
Step of identifying a master receive data phase value to coordinate the transfer of data from …
Step of identifying a master receive data phase value to coordinate the transfer of data from …
Micro-threaded memory
FA Ware, CE Hampel, WS Richardson… - US Patent …, 2013 - Google Patents
A micro-threaded memory device. A plurality of storage banks are provided, each including
a plurality of rows of storage cells and having an access restriction in that at least a minimum …
a plurality of rows of storage cells and having an access restriction in that at least a minimum …
The response of composite joints with bolt-clam** loads, part II: model verification
HT Sun, FK Chang, X Qing - Journal of Composite Materials, 2002 - journals.sagepub.com
Extensive experiments were performed to characterize the material response due to bearing
failure in composite bolted joints with and without lateral clamp-up supports. Composite …
failure in composite bolted joints with and without lateral clamp-up supports. Composite …
Periodic interface calibration for high speed communication
JM Kizer - US Patent 7,072,355, 2006 - Google Patents
A high-speed communication interface manages a parallel bus having N bus lines. N+ 1
communication lines are established. A maintenance operation is performed on one of the …
communication lines are established. A maintenance operation is performed on one of the …
Communication channel calibration for drift conditions
FA Ware, RE Perego, CE Hampel - US Patent 7,095,789, 2006 - Google Patents
(57) ABSTRACT A method and system provides for execution of calibration cycles from time
to time during normal operation of the communication channel. A calibration cycle includes …
to time during normal operation of the communication channel. A calibration cycle includes …
Hybrid wired and wireless chip-to-chip communications
SC Best - US Patent 7,535,958, 2009 - Google Patents
A hybrid wireless and wired system distributes precise timing and synchronization
information among the nodes over a wired interconnect structure while data is transmitted …
information among the nodes over a wired interconnect structure while data is transmitted …
Multi-column addressing mode memory system including an integrated circuit memory device
FA Ware, L Lai, CA Bellows, WS Richardson - US Patent 8,050,134, 2011 - Google Patents
A memory system includes a master device, such as a graphics controller or processor, and
an integrated circuit memory device operable in a dual column addressing mode. The …
an integrated circuit memory device operable in a dual column addressing mode. The …
Drift tracking feedback for communication channels
SC Best, AM Abhyankar, KY Chang… - US Patent …, 2005 - Google Patents
A communication channel includes a first component having a transmitter coupled to a
normal signal source, and a second component having a receiver coupled to a normal …
normal signal source, and a second component having a receiver coupled to a normal …
Periodic calibration for communication channels by drift tracking
CE Hampel, FA Ware, RE Perego - US Patent 7,400,670, 2008 - Google Patents
A method and system that provides for execution of a first calibration sequence, such as
upon initialization of a system, to establish an operation value, which utilizes an algorithm …
upon initialization of a system, to establish an operation value, which utilizes an algorithm …