A 28-nm compute SRAM with bit-serial logic/arithmetic operations for programmable in-memory vector computing
This article proposes a general-purpose hybrid in-/near-memory compute SRAM (CRAM)
that combines an 8T transposable bit cell with vector-based, bit-serial in-memory arithmetic …
that combines an 8T transposable bit cell with vector-based, bit-serial in-memory arithmetic …
Hardware implementation of SLAM algorithms: a survey on implementation approaches and platforms
Simultaneous localization and map** (SLAM) is an active research topic in machine
vision and robotics. It has various applications in many different fields such as mobile robots …
vision and robotics. It has various applications in many different fields such as mobile robots …
Timely: Pushing data movements and interfaces in pim accelerators towards local and in time domain
Resistive-random-access-memory (ReRAM) based processing-in-memory (R2PIM)
accelerators show promise in bridging the gap between Internet of Thing devices' …
accelerators show promise in bridging the gap between Internet of Thing devices' …
Smartexchange: Trading higher-cost memory storage/access for lower-cost computation
We present SmartExchange, an algorithm-hardware co-design framework to trade higher-
cost memory storage/access for lower-cost computation, for energy-efficient inference of …
cost memory storage/access for lower-cost computation, for energy-efficient inference of …
A 4.29 nJ/pixel stereo depth coprocessor with pixel level pipeline and region optimized semi-global matching for IoT application
The semi-global matching (SGM) algorithm in stereo vision is a well-known depth-estimation
method since it can generate dense and robust disparity maps. However, the real-time …
method since it can generate dense and robust disparity maps. However, the real-time …
An ultra-low-power image signal processor for hierarchical image recognition with deep neural networks
H An, S Schiferl, S Venkatesan… - IEEE Journal of Solid …, 2020 - ieeexplore.ieee.org
We propose an ultra-low-power (ULP) image signal processor (ISP) that performs on-the-fly
in-processing frame compression/decompression and hierarchical event recognition to …
in-processing frame compression/decompression and hierarchical event recognition to …
[HTML][HTML] Imperceptible–visible watermarking to information security tasks in color imaging
Digital image watermarking algorithms have been designed for intellectual property,
copyright protection, medical data management, and other related fields; furthermore, in real …
copyright protection, medical data management, and other related fields; furthermore, in real …
A block PatchMatch-based energy-resource efficient stereo matching processor on FPGA
This paper presents a field programmable gate array (FPGA)-based, high-performance and
energy-resource efficient stereo matching processor. The proposed processor executes …
energy-resource efficient stereo matching processor. The proposed processor executes …
CV-CIM: A Hybrid Domain Xor-Derived Similarity-Aware Computation-in-Memory Supporting Cost–Volume Construction
Cost–volume construction, a cornerstone of stereo vision processing, has been widely
utilized across diverse domains such as robotics, autonomous vehicles, 3-D reconstruction …
utilized across diverse domains such as robotics, autonomous vehicles, 3-D reconstruction …
A low-cost high-speed object tracking VLSI system based on unified textural and dynamic compressive features
W He, J Zhang, Y Lin, X Zhou, P Li, L Liu… - … on Circuits and …, 2020 - ieeexplore.ieee.org
Real-time object tracking is demanded in versatile embedded computer vision applications.
To this end, a low-cost high-speed VLSI system is proposed for object tracking, based on …
To this end, a low-cost high-speed VLSI system is proposed for object tracking, based on …