[BOOK][B] Design for embedded image processing on FPGAs
DG Bailey - 2023 - books.google.com
Design for Embedded Image Processing on FPGAs Bridge the gap between software and
hardware with this foundational design reference Field-programmable gate arrays (FPGAs) …
hardware with this foundational design reference Field-programmable gate arrays (FPGAs) …
Influence of Image TIFF Format and JPEG Compression Level in the Accuracy of the 3D Model and Quality of the Orthophoto in UAV Photogrammetry
The aim of this study is to evaluate the degradation of the accuracy and quality of the images
in relation to the TIFF format and the different compression level of the JPEG format …
in relation to the TIFF format and the different compression level of the JPEG format …
Quick (and dirty) aggregate queries on low-power WANs
Low-Power Wide-Area Networks (LP-WANs) are seeing wide-spread deployments
connecting millions of sensors, each powered by a ten-year AA battery to radio …
connecting millions of sensors, each powered by a ten-year AA battery to radio …
FPGA implementation of pipelined 2D-DCT and quantization architecture for JPEG image compression
ED Kusuma, TS Widodo - 2010 International symposium on …, 2010 - ieeexplore.ieee.org
Two dimensional DCT takes important role in JPEG image compression. Architecture and
VHDL design of 2-D DCT, combined with quantization and zig-zag arrangement, is …
VHDL design of 2-D DCT, combined with quantization and zig-zag arrangement, is …
imDedup: A lossless deduplication scheme to eliminate fine-grained redundancy among images
Images occupy a large amount of storage in data centers. To cope with the explosive growth
of the image storage requirement, image compression techniques are devised to shrink the …
of the image storage requirement, image compression techniques are devised to shrink the …
A pipelined fast 2D-DCT accelerator for FPGA-based SoCs
Multimedia applications, and in particular the encoding and decoding of standard image and
video formats, are usually a typical target for systems-on-chip (SoC). The bi-dimensional …
video formats, are usually a typical target for systems-on-chip (SoC). The bi-dimensional …
A digital watermarking encryption technique based on FPGA cloud accelerator
Y Cao, F Yu, Y Tang - IEEE Access, 2020 - ieeexplore.ieee.org
Digital watermarking has the properties such as invisibility and anti-aggression, so the
digital watermarking technology has been widely used in copyright protection, information …
digital watermarking technology has been widely used in copyright protection, information …
A high performance video transform engine by using space-time scheduling strategy
YH Chen, TY Chang - IEEE transactions on very large scale …, 2011 - ieeexplore.ieee.org
In this paper, a spatial and time scheduling strategy, called the space-time scheduling (STS)
strategy, that achieves high image resolutions in real-time systems is proposed. The …
strategy, that achieves high image resolutions in real-time systems is proposed. The …
Energy-efficient Hadamard-based SATD hardware architectures through calculation reuse
The Hadamard-based Sum of Absolute Transformed Differences (SATD) is a distortion
metric that correlates better with other video encoding steps than the commonly used Sum of …
metric that correlates better with other video encoding steps than the commonly used Sum of …
Small-size algorithms for the type-I discrete cosine transform with reduced complexity
M Kolenderski, A Cariow - Electronics, 2022 - mdpi.com
Discrete cosine transforms (DCTs) are widely used in intelligent electronic systems for data
storage, processing, and transmission. The popularity of using these transformations, on the …
storage, processing, and transmission. The popularity of using these transformations, on the …