Coarse grained reconfigurable architectures in the past 25 years: Overview and classification
M Wijtvliet, L Waeijen… - … Conference on Embedded …, 2016 - ieeexplore.ieee.org
Reconfigurable architectures become more popular now general purpose compute
performance does not increase as rapidly as before. Field programmable gate arrays are …
performance does not increase as rapidly as before. Field programmable gate arrays are …
Dryad: distributed data-parallel programs from sequential building blocks
Dryad is a general-purpose distributed execution engine for coarse-grain data-parallel
applications. A Dryad application combines computational" vertices" with communication" …
applications. A Dryad application combines computational" vertices" with communication" …
Brook for GPUs: stream computing on graphics hardware
I Buck, T Foley, D Horn, J Sugerman… - ACM transactions on …, 2004 - dl.acm.org
In this paper, we present Brook for GPUs, a system for general-purpose computation on
programmable graphics hardware. Brook extends C to include simple data-parallel …
programmable graphics hardware. Brook extends C to include simple data-parallel …
[LIBRO][B] FPGA-based implementation of signal processing systems
R Woods, J McAllister, G Lightbody, Y Yi - 2008 - books.google.com
Field programmable gate arrays (FPGAs) are an increasingly popular technology for
implementing digital signal processing (DSP) systems. By allowing designers to create …
implementing digital signal processing (DSP) systems. By allowing designers to create …
Sequoia: Programming the memory hierarchy
K Fatahalian, DR Horn, TJ Knight, L Leem… - Proceedings of the …, 2006 - dl.acm.org
We present Sequoia, a programming language designed to facilitate the development of
memory hierarchy aware parallel programs that remain portable across modern machines …
memory hierarchy aware parallel programs that remain portable across modern machines …
Cg: A system for programming graphics hardware in a C-like language
The latest real-time graphics architectures include programmable floating-point vertex and
fragment processors, with support for data-dependent control flow in the vertex processor …
fragment processors, with support for data-dependent control flow in the vertex processor …
[CITAS][C] Hierarchical Neural Networks for Image Interpretation
S Behnke - 2003 - books.google.com
Human performance in visual perception by far exceeds the performance of contemporary
computer vision systems. While humans are able to perceive their environment almost …
computer vision systems. While humans are able to perceive their environment almost …
Evaluation of the Raw microprocessor: An exposed-wire-delay architecture for ILP and streams
This paper evaluates the Raw microprocessor. Raw addresses thechallenge of building a
general-purpose architecture that performswell on a larger class of stream and embedded …
general-purpose architecture that performswell on a larger class of stream and embedded …
RPU: a programmable ray processing unit for realtime ray tracing
S Woop, J Schmittler, P Slusallek - ACM Transactions on Graphics (TOG), 2005 - dl.acm.org
Recursive ray tracing is a simple yet powerful and general approach for accurately
computing global light transport and rendering high quality images. While recent algorithmic …
computing global light transport and rendering high quality images. While recent algorithmic …
Understanding throughput-oriented architectures
M Garland, DB Kirk - Communications of the ACM, 2010 - dl.acm.org
Understanding throughput-oriented architectures Page 1 58 communications of the acm |
november 2010 | vol. 53 | no. 11 contributed articles understanding throughputoriented …
november 2010 | vol. 53 | no. 11 contributed articles understanding throughputoriented …