Clock-gating has been employed in low-power FPGA designs based on an emulated and
compromised method. So far in literature the actual efficiency of savings in power …

This paper presents experimental measurements of power consumption using different
techniques to turn off part of a system and switch between active and standby modes. The …

Fault tolerance is explored for spacecraft computers employing Field-Programmable Gate
Arrays (FPGAs). Techniques are investigated for tolerating Single Event Upsets (SEUs) …

This paper describes an approach for develo** energy-optimized run-time reconfigurable
designs which benefit from clock gating. The approach is applied to two techniques …

The main aim of this work is to study and show power reduction by using clock gating
techniques with pulse enable concept. In this two 8 bit input data and a MUX 4: 1 for …

We present a highly efficient automated clock gating platform for rapidly develo** power
efficient hardware architectures. Our language, called CoDeL, allows hardware description …

A novel baseband-processor for LF RFID tag compatible with ISOl 1784/11785 is presented.
An asynchronous method for data demodulation is proposed to solve the clock halting …

This paper describes a method of develo** energy-efficient run-time reconfigurable
hardware designs. The key idea is to systematically deactivate part of the hardware using …

Although various techniques have been proposed for power reduction in field-
programmable devices (FPDs), they are still all based on conventional logic elements (LEs) …

Power dissipation in CMOS circuits is of growing concern as the computational requirements
of portable, battery operated devices increases. The ability to easily develop application …