Efficient 2D DCT architecture based on approximate compressors for image compression with HEVC intra-prediction

A Akman, S Cekli - Journal of Real-Time Image Processing, 2023 - Springer
This study presents a design of two-dimensional (2D) discrete cosine transform (DCT)
architecture to be used with high-efficiency video coding (HEVC) intra-prediction method in …

Video coding and processing: a survey

Y Liu, S Liu, Y Wang, H Zhao - Neurocomputing, 2020 - Elsevier
Vision is the main way for people to perceive and recognize the world. In this paper, four
categories of the redundant information of video encoding, spatial redundancy, time …

A low-power spike-like neural network design

M Losh, D Llamocca - Electronics, 2019 - mdpi.com
Modern massively-parallel Graphics Processing Units (GPUs) and Machine Learning (ML)
frameworks enable neural network implementations of unprecedented performance and …

Enhanced holoentropy-based encoding via whale optimization for highly efficient video coding

V Munagala, SP Kodati - The Visual Computer, 2021 - Springer
High-efficiency video coding (HEVC), a video compression method is considered as the
most capable descendant of the extensively deployed advanced VC (AVC). Compared with …

Dynamically reconfigurable deep learning for efficient video processing in smart IoT systems

O Eldash, A Frost, K Khalil, A Kumar… - 2020 IEEE 6th World …, 2020 - ieeexplore.ieee.org
Video systems are the core of many IoT systems, and efficient processing is crucial for their
operation. There is little work focusing on the flexibility of current hardware systems when …

Energy‐efficient system‐on‐chip reconfigurable architecture design for sum of absolute difference computation in motion estimation process of H. 265/HEVC video …

KRS Chandran… - … and Computation: Practice …, 2022 - Wiley Online Library
Motion estimation is the important and computationally intensive part of any video encoding.
The objective of this paper is to design and analyze the coarse and fine reconfiguration of …

Fly-inspired edge detection: Architecture and reconfigurable embedded implementation

ON Adabonyan, D Llamocca… - 2018 IEEE 61st …, 2018 - ieeexplore.ieee.org
This work presents a reconfigurable embedded implementation of a fly-inspired edge
detection algorithm that allows for run-time alteration of the numerical format in response to …

A speed and energy focused framework for dynamic hardware reconfiguration

K Khalil, O Eldash, A Kumar… - 2019 32nd IEEE …, 2019 - ieeexplore.ieee.org
The current trends in Integrated Circuits are driven by the best utilization of the rapidly
saturating and costly technologies. One of such endeavors is to build a self-adaptive …

Diseño de la arquitectura de transformada discreta directa e inversa del coseno para un decodificador HEVC

MA Portocarrero Rodriguez - 2018 - tesis.pucp.edu.pe
El empleo de video de alta resolución es una actividad muy común en la actualidad, debido
a la existencia de dispositivos portátiles capaces de reproducir y crear secuencias de video …

An Architecture for Real-Time Estimation of Crank-Angle-Resolved Engine Cylinder Pressure

J Wu, A Jacoby, D Llamocca… - 2018 IEEE International …, 2018 - ieeexplore.ieee.org
This work presents a custom hardware architecture for crank-angle-resolved engine cylinder
pressure estimation that can accept inputs such as speed, manifold pressure and throttle …