[LIBRO][B] VLSI physical design: from graph partitioning to timing closure
The electronic design automation (EDA) industry develops software to support engineers in
the creation of new integrated circuit (IC) designs. Due to the high complexity of modern …
the creation of new integrated circuit (IC) designs. Due to the high complexity of modern …
The policy-gradient placement and generative routing neural networks for chip design
Placement and routing are two critical yet time-consuming steps of chip design in modern
VLSI systems. Distinct from traditional heuristic solvers, this paper on one hand proposes an …
VLSI systems. Distinct from traditional heuristic solvers, this paper on one hand proposes an …
A deep reinforcement learning approach for global routing
Global routing has been a historically challenging problem in the electronic circuit design,
where the challenge is to connect a large and arbitrary number of circuit components with …
where the challenge is to connect a large and arbitrary number of circuit components with …
FastRoute 4.0: Global router with efficient via minimization
Y Xu, Y Zhang, C Chu - 2009 Asia and South Pacific Design …, 2009 - ieeexplore.ieee.org
The number of vias generated during the global routing stage is a critical factor for the yield
of final circuits. However, most global routers only approach the problem by charging a cost …
of final circuits. However, most global routers only approach the problem by charging a cost …
Towards machine learning for placement and routing in chip design: a methodological overview
Placement and routing are two indispensable and challenging (NP-hard) tasks in modern
chip design flows. Compared with traditional solvers using heuristics or expert-well …
chip design flows. Compared with traditional solvers using heuristics or expert-well …
High-performance routing at the nanometer scale
In this paper, we describe significant improvements to core routing technologies and
outperform the best results from the International Symposium on Physical Design 2007 …
outperform the best results from the International Symposium on Physical Design 2007 …
MaizeRouter: Engineering an Effective Global Router
MD Moffitt - IEEE Transactions on Computer-Aided Design of …, 2008 - ieeexplore.ieee.org
In this paper, we present the complete design and architectural details of MaizeRouter.
MaizeRouter reflects a significant leap in progress over existing publicly available routing …
MaizeRouter reflects a significant leap in progress over existing publicly available routing …
Understanding graphs in EDA: From shallow to deep learning
As the scale of integrated circuits keeps increasing, it is witnessed that there is a surge in the
research of electronic design automation (EDA) to make the technology node scaling …
research of electronic design automation (EDA) to make the technology node scaling …
FastRoute 2.0: A high-quality and efficient global router
M Pan, C Chu - 2007 Asia and south pacific design automation …, 2007 - ieeexplore.ieee.org
Because of the increasing dominance of interconnect issues in advanced IC technology, it is
desirable to incorporate global routing into early design stages to get accurate interconnect …
desirable to incorporate global routing into early design stages to get accurate interconnect …
The ISPD-2011 routability-driven placement contest and benchmark suite
The last few years have seen significant advances in the quality of placement algorithms.
This is in part due to the availability of large, challenging testcases by way of the ISPD-2005 …
This is in part due to the availability of large, challenging testcases by way of the ISPD-2005 …