Pulsed high-density plasmas for advanced dry etching processes
Plasma etching processes at the 22 nm technology node and below will have to satisfy
multiple stringent scaling requirements of microelectronics fabrication. To satisfy these …
multiple stringent scaling requirements of microelectronics fabrication. To satisfy these …
Radiation effects in advanced multiple gate and silicon-on-insulator transistors
E Simoen, M Gaillardin, P Paillet… - … on Nuclear Science, 2013 - ieeexplore.ieee.org
The aim of this review paper is to describe in a comprehensive manner the current
understanding of the radiation response of state-of-the-art Silicon-on-Insulator (SOI) and …
understanding of the radiation response of state-of-the-art Silicon-on-Insulator (SOI) and …
Strained Si and SiGe nanowire tunnel FETs for logic and analog applications
QT Zhao, S Richter, C Schulte-Braucks… - IEEE Journal of the …, 2015 - ieeexplore.ieee.org
Guided by the Wentzel-Kramers–Brillouin approximation for band-to-band tunneling (BTBT),
various performance boosters for Si TFETs are presented and experimentally verified. Along …
various performance boosters for Si TFETs are presented and experimentally verified. Along …
SiGe channel technology: Superior reliability toward ultrathin EOT devices—Part I: NBTI
We report extensive experimental results of the negative bias temperature instability (NBTI)
reliability of SiGe channel pMOSFETs as a function of the main gate-stack parameters. The …
reliability of SiGe channel pMOSFETs as a function of the main gate-stack parameters. The …
A robust and write bit-line free sub-threshold 12T-SRAM for ultra low power applications in 14 nm FinFET technology
In this paper, a robust 12T-SRAM memory cell at sub-threshold voltage is designed to
reduce power consumption for low power applications, that in addition to reducing power …
reduce power consumption for low power applications, that in addition to reducing power …
Total-Ionizing-Dose Effects and Low-Frequency Noise in 30-nm Gate-Length Bulk and SOI FinFETs With SiO2/HfO2 Gate Dielectrics
Total-ionizing-dose (TID) effects and low-frequency noise are evaluated in 30-nm gate-
length bulk and silicon-on-insulator (SOI) FinFETs for devices with fin widths of 10-40 nm …
length bulk and silicon-on-insulator (SOI) FinFETs for devices with fin widths of 10-40 nm …
Device and circuit exploration of multi-nanosheet transistor for sub-3 nm technology node
Y Seon, J Chang, C Yoo, J Jeon - Electronics, 2021 - mdpi.com
A multi-nanosheet field-effect transistor (mNS-FET) device was developed to maximize gate
controllability while making the channel in the form of a sheet. The mNS-FET has superior …
controllability while making the channel in the form of a sheet. The mNS-FET has superior …
Impact of single charged gate oxide defects on the performance and scaling of nanoscaled FETs
We report extensive statistical NBTI reliability measurements of nanoscaled FETs of different
technologies, based on which we propose a 1/area scaling rule for the statistical impact of …
technologies, based on which we propose a 1/area scaling rule for the statistical impact of …
A write bit-line free sub-threshold SRAM cell with fully half-select free feature and high reliability for ultra-low power applications
In this paper, a robust sub-threshold 13 T-SRAM cell is designed, which in addition to
reducing power and energy consumption can show high reliability and have the least error …
reducing power and energy consumption can show high reliability and have the least error …
Laser-and heavy ion-induced charge collection in bulk FinFETs
F El-Mamouni, EX Zhang, ND Pate… - … on Nuclear Science, 2011 - ieeexplore.ieee.org
Through-wafer two-photon absorption laser experiments were performed on bulk FinFETs.
Transients show distinct signatures for charge collection from drift and diffusion …
Transients show distinct signatures for charge collection from drift and diffusion …